Lines Matching defs:pxa3xx_nand_info
179 struct pxa3xx_nand_info { struct
180 struct nand_hw_control controller;
181 struct platform_device *pdev;
183 struct clk *clk;
184 void __iomem *mmio_base;
185 unsigned long mmio_phys;
186 struct completion cmd_complete, dev_ready;
188 unsigned int buf_start;
189 unsigned int buf_count;
190 unsigned int buf_size;
191 unsigned int data_buff_pos;
192 unsigned int oob_buff_pos;
195 int drcmr_dat;
196 int drcmr_cmd;
198 unsigned char *data_buff;
199 unsigned char *oob_buff;
200 dma_addr_t data_buff_phys;
201 int data_dma_ch;
202 struct pxa_dma_desc *data_desc;
203 dma_addr_t data_desc_addr;
205 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
206 unsigned int state;
212 enum pxa3xx_nand_variant variant;
214 int cs;
215 int use_ecc; /* use HW ECC ? */
216 int ecc_bch; /* using BCH ECC? */
217 int use_dma; /* use DMA ? */
218 int use_spare; /* use spare ? */
219 int need_wait;
221 unsigned int data_size; /* data to be read from FIFO */
222 unsigned int chunk_size; /* split commands chunk size */
223 unsigned int oob_size;
224 unsigned int spare_size;
225 unsigned int ecc_size;
226 unsigned int ecc_err_cnt;
227 unsigned int max_bitflips;
228 int retcode;
231 uint32_t reg_ndcr;
232 uint32_t ndtr0cs0;
233 uint32_t ndtr1cs0;
236 uint32_t ndcb0;
237 uint32_t ndcb1;
238 uint32_t ndcb2;
239 uint32_t ndcb3;