323 		dev_dbg(priv->dev,  in fsl_elbc_cmdfunc()
503 		dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");  in fsl_elbc_cmdfunc()
637 	dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",  in fsl_elbc_chip_init_tail()
639 	dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",  in fsl_elbc_chip_init_tail()
641 	dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",  in fsl_elbc_chip_init_tail()
643 	dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",  in fsl_elbc_chip_init_tail()
645 	dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",  in fsl_elbc_chip_init_tail()
647 	dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",  in fsl_elbc_chip_init_tail()
649 	dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",  in fsl_elbc_chip_init_tail()
651 	dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",  in fsl_elbc_chip_init_tail()
653 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",  in fsl_elbc_chip_init_tail()
655 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",  in fsl_elbc_chip_init_tail()
657 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",  in fsl_elbc_chip_init_tail()
659 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",  in fsl_elbc_chip_init_tail()
661 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",  in fsl_elbc_chip_init_tail()
663 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);  in fsl_elbc_chip_init_tail()
664 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);  in fsl_elbc_chip_init_tail()
665 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",  in fsl_elbc_chip_init_tail()
667 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",  in fsl_elbc_chip_init_tail()
669 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",  in fsl_elbc_chip_init_tail()
746 	dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);  in fsl_elbc_chip_init()