Lines Matching refs:info
86 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info, in davinci_nand_readl() argument
89 return __raw_readl(info->base + offset); in davinci_nand_readl()
92 static inline void davinci_nand_writel(struct davinci_nand_info *info, in davinci_nand_writel() argument
95 __raw_writel(value, info->base + offset); in davinci_nand_writel()
107 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_hwcontrol() local
108 uint32_t addr = info->current_cs; in nand_davinci_hwcontrol()
114 addr |= info->mask_cle; in nand_davinci_hwcontrol()
116 addr |= info->mask_ale; in nand_davinci_hwcontrol()
127 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_select_chip() local
128 uint32_t addr = info->ioaddr; in nand_davinci_select_chip()
132 addr |= info->mask_chipsel; in nand_davinci_select_chip()
133 info->current_cs = addr; in nand_davinci_select_chip()
135 info->chip.IO_ADDR_W = (void __iomem __force *)addr; in nand_davinci_select_chip()
136 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W; in nand_davinci_select_chip()
147 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_readecc_1bit() local
149 return davinci_nand_readl(info, NANDF1ECC_OFFSET in nand_davinci_readecc_1bit()
150 + 4 * info->core_chipsel); in nand_davinci_readecc_1bit()
155 struct davinci_nand_info *info; in nand_davinci_hwctl_1bit() local
159 info = to_davinci_nand(mtd); in nand_davinci_hwctl_1bit()
167 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET); in nand_davinci_hwctl_1bit()
168 nandcfr |= BIT(8 + info->core_chipsel); in nand_davinci_hwctl_1bit()
169 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr); in nand_davinci_hwctl_1bit()
240 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_hwctl_4bit() local
247 val = davinci_nand_readl(info, NANDFCR_OFFSET); in nand_davinci_hwctl_4bit()
249 val |= (info->core_chipsel << 4) | BIT(12); in nand_davinci_hwctl_4bit()
250 davinci_nand_writel(info, NANDFCR_OFFSET, val); in nand_davinci_hwctl_4bit()
252 info->is_readmode = (mode == NAND_ECC_READ); in nand_davinci_hwctl_4bit()
259 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) in nand_davinci_readecc_4bit() argument
263 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; in nand_davinci_readecc_4bit()
264 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; in nand_davinci_readecc_4bit()
265 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; in nand_davinci_readecc_4bit()
266 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; in nand_davinci_readecc_4bit()
273 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_calculate_4bit() local
282 if (info->is_readmode) { in nand_davinci_calculate_4bit()
283 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); in nand_davinci_calculate_4bit()
292 nand_davinci_readecc_4bit(info, raw_ecc); in nand_davinci_calculate_4bit()
311 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_correct_4bit() local
345 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); in nand_davinci_correct_4bit()
350 davinci_nand_readl(info, NANDFSR_OFFSET); in nand_davinci_correct_4bit()
351 nand_davinci_readecc_4bit(info, syndrome); in nand_davinci_correct_4bit()
359 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); in nand_davinci_correct_4bit()
365 davinci_nand_writel(info, NANDFCR_OFFSET, in nand_davinci_correct_4bit()
366 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); in nand_davinci_correct_4bit()
379 ecc_state = (davinci_nand_readl(info, in nand_davinci_correct_4bit()
385 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); in nand_davinci_correct_4bit()
389 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); in nand_davinci_correct_4bit()
392 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); in nand_davinci_correct_4bit()
410 error_address = davinci_nand_readl(info, in nand_davinci_correct_4bit()
412 error_value = davinci_nand_readl(info, in nand_davinci_correct_4bit()
415 error_address = davinci_nand_readl(info, in nand_davinci_correct_4bit()
417 error_value = davinci_nand_readl(info, in nand_davinci_correct_4bit()
479 struct davinci_nand_info *info = to_davinci_nand(mtd); in nand_davinci_dev_ready() local
481 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); in nand_davinci_dev_ready()
605 struct davinci_nand_info *info; in nand_davinci_probe() local
626 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in nand_davinci_probe()
627 if (!info) in nand_davinci_probe()
630 platform_set_drvdata(pdev, info); in nand_davinci_probe()
655 info->dev = &pdev->dev; in nand_davinci_probe()
656 info->base = base; in nand_davinci_probe()
657 info->vaddr = vaddr; in nand_davinci_probe()
659 info->mtd.priv = &info->chip; in nand_davinci_probe()
660 info->mtd.name = dev_name(&pdev->dev); in nand_davinci_probe()
661 info->mtd.owner = THIS_MODULE; in nand_davinci_probe()
663 info->mtd.dev.parent = &pdev->dev; in nand_davinci_probe()
665 info->chip.IO_ADDR_R = vaddr; in nand_davinci_probe()
666 info->chip.IO_ADDR_W = vaddr; in nand_davinci_probe()
667 info->chip.chip_delay = 0; in nand_davinci_probe()
668 info->chip.select_chip = nand_davinci_select_chip; in nand_davinci_probe()
671 info->chip.bbt_options = pdata->bbt_options; in nand_davinci_probe()
673 info->chip.options = pdata->options; in nand_davinci_probe()
674 info->chip.bbt_td = pdata->bbt_td; in nand_davinci_probe()
675 info->chip.bbt_md = pdata->bbt_md; in nand_davinci_probe()
676 info->timing = pdata->timing; in nand_davinci_probe()
678 info->ioaddr = (uint32_t __force) vaddr; in nand_davinci_probe()
680 info->current_cs = info->ioaddr; in nand_davinci_probe()
681 info->core_chipsel = pdev->id; in nand_davinci_probe()
682 info->mask_chipsel = pdata->mask_chipsel; in nand_davinci_probe()
685 info->mask_ale = pdata->mask_ale ? : MASK_ALE; in nand_davinci_probe()
686 info->mask_cle = pdata->mask_cle ? : MASK_CLE; in nand_davinci_probe()
689 info->chip.cmd_ctrl = nand_davinci_hwcontrol; in nand_davinci_probe()
690 info->chip.dev_ready = nand_davinci_dev_ready; in nand_davinci_probe()
693 info->chip.read_buf = nand_davinci_read_buf; in nand_davinci_probe()
694 info->chip.write_buf = nand_davinci_write_buf; in nand_davinci_probe()
722 info->chip.ecc.calculate = nand_davinci_calculate_4bit; in nand_davinci_probe()
723 info->chip.ecc.correct = nand_davinci_correct_4bit; in nand_davinci_probe()
724 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; in nand_davinci_probe()
725 info->chip.ecc.bytes = 10; in nand_davinci_probe()
727 info->chip.ecc.calculate = nand_davinci_calculate_1bit; in nand_davinci_probe()
728 info->chip.ecc.correct = nand_davinci_correct_1bit; in nand_davinci_probe()
729 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; in nand_davinci_probe()
730 info->chip.ecc.bytes = 3; in nand_davinci_probe()
732 info->chip.ecc.size = 512; in nand_davinci_probe()
733 info->chip.ecc.strength = pdata->ecc_bits; in nand_davinci_probe()
738 info->chip.ecc.mode = ecc_mode; in nand_davinci_probe()
740 info->clk = devm_clk_get(&pdev->dev, "aemif"); in nand_davinci_probe()
741 if (IS_ERR(info->clk)) { in nand_davinci_probe()
742 ret = PTR_ERR(info->clk); in nand_davinci_probe()
747 ret = clk_prepare_enable(info->clk); in nand_davinci_probe()
757 val = davinci_nand_readl(info, NANDFCR_OFFSET); in nand_davinci_probe()
758 val |= BIT(info->core_chipsel); in nand_davinci_probe()
759 davinci_nand_writel(info, NANDFCR_OFFSET, val); in nand_davinci_probe()
764 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL); in nand_davinci_probe()
776 int chunks = info->mtd.writesize / 512; in nand_davinci_probe()
778 if (!chunks || info->mtd.oobsize < 16) { in nand_davinci_probe()
789 info->ecclayout = hwecc4_small; in nand_davinci_probe()
790 info->ecclayout.oobfree[1].length = in nand_davinci_probe()
791 info->mtd.oobsize - 16; in nand_davinci_probe()
795 info->ecclayout = hwecc4_2048; in nand_davinci_probe()
796 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; in nand_davinci_probe()
815 info->chip.ecc.layout = &info->ecclayout; in nand_davinci_probe()
818 ret = nand_scan_tail(&info->mtd); in nand_davinci_probe()
823 ret = mtd_device_parse_register(&info->mtd, NULL, NULL, in nand_davinci_probe()
829 ret = mtd_device_parse_register(&info->mtd, NULL, &ppdata, in nand_davinci_probe()
835 val = davinci_nand_readl(info, NRCSR_OFFSET); in nand_davinci_probe()
842 clk_disable_unprepare(info->clk); in nand_davinci_probe()
854 struct davinci_nand_info *info = platform_get_drvdata(pdev); in nand_davinci_remove() local
857 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) in nand_davinci_remove()
861 nand_release(&info->mtd); in nand_davinci_remove()
863 clk_disable_unprepare(info->clk); in nand_davinci_remove()