253 	u32 rval;  in sunxi_mmc_reset_host()  local
257 		rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_reset_host()
258 	} while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));  in sunxi_mmc_reset_host()
260 	if (rval & SDXC_HARDWARE_RESET) {  in sunxi_mmc_reset_host()
270 	u32 rval;  in sunxi_mmc_init_host()  local
284 	rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_init_host()
285 	rval |= SDXC_INTERRUPT_ENABLE_BIT;  in sunxi_mmc_init_host()
286 	rval &= ~SDXC_ACCESS_DONE_DIRECT;  in sunxi_mmc_init_host()
287 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_init_host()
361 	u32 rval;  in sunxi_mmc_start_dma()  local
365 	rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_start_dma()
366 	rval |= SDXC_DMA_ENABLE_BIT;  in sunxi_mmc_start_dma()
367 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_start_dma()
368 	rval |= SDXC_DMA_RESET;  in sunxi_mmc_start_dma()
369 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_start_dma()
450 	u32 rval;  in sunxi_mmc_finalize_request()  local
483 		rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_finalize_request()
484 		rval |= SDXC_DMA_RESET;  in sunxi_mmc_finalize_request()
485 		mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_finalize_request()
486 		rval &= ~SDXC_DMA_ENABLE_BIT;  in sunxi_mmc_finalize_request()
487 		mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_finalize_request()
488 		rval |= SDXC_FIFO_RESET;  in sunxi_mmc_finalize_request()
489 		mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_finalize_request()
599 	u32 rval;  in sunxi_mmc_oclk_onoff()  local
601 	rval = mmc_readl(host, REG_CLKCR);  in sunxi_mmc_oclk_onoff()
602 	rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);  in sunxi_mmc_oclk_onoff()
605 		rval |= SDXC_CARD_CLOCK_ON;  in sunxi_mmc_oclk_onoff()
607 	mmc_writel(host, REG_CLKCR, rval);  in sunxi_mmc_oclk_onoff()
609 	rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;  in sunxi_mmc_oclk_onoff()
610 	mmc_writel(host, REG_CMDR, rval);  in sunxi_mmc_oclk_onoff()
613 		rval = mmc_readl(host, REG_CMDR);  in sunxi_mmc_oclk_onoff()
614 	} while (time_before(jiffies, expire) && (rval & SDXC_START));  in sunxi_mmc_oclk_onoff()
620 	if (rval & SDXC_START) {  in sunxi_mmc_oclk_onoff()
631 	u32 rate, oclk_dly, rval, sclk_dly;  in sunxi_mmc_clk_set_rate()  local
651 	rval = mmc_readl(host, REG_CLKCR);  in sunxi_mmc_clk_set_rate()
652 	rval &= ~0xff;  in sunxi_mmc_clk_set_rate()
653 	mmc_writel(host, REG_CLKCR, rval);  in sunxi_mmc_clk_set_rate()
689 	u32 rval;  in sunxi_mmc_set_ios()  local
727 	rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_set_ios()
729 		rval |= SDXC_DDR_MODE;  in sunxi_mmc_set_ios()
731 		rval &= ~SDXC_DDR_MODE;  in sunxi_mmc_set_ios()
732 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_set_ios()