Lines Matching refs:scratch_32

26 	u32 scratch_32;  in o2_pci_set_baseclk()  local
28 O2_SD_PLL_SETTING, &scratch_32); in o2_pci_set_baseclk()
30 scratch_32 &= 0x0000FFFF; in o2_pci_set_baseclk()
31 scratch_32 |= value; in o2_pci_set_baseclk()
34 O2_SD_PLL_SETTING, scratch_32); in o2_pci_set_baseclk()
40 u32 scratch_32; in o2_pci_led_enable() local
44 O2_SD_FUNC_REG0, &scratch_32); in o2_pci_led_enable()
48 scratch_32 &= ~O2_SD_FREG0_LEDOFF; in o2_pci_led_enable()
50 O2_SD_FUNC_REG0, scratch_32); in o2_pci_led_enable()
53 O2_SD_TEST_REG, &scratch_32); in o2_pci_led_enable()
57 scratch_32 |= O2_SD_LED_ENABLE; in o2_pci_led_enable()
59 O2_SD_TEST_REG, scratch_32); in o2_pci_led_enable()
65 u32 scratch_32; in sdhci_pci_o2_fujin2_pci_init() local
68 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
71 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); in sdhci_pci_o2_fujin2_pci_init()
72 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
75 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
78 scratch_32 &= ~((1 << 19) | (1 << 11)); in sdhci_pci_o2_fujin2_pci_init()
79 scratch_32 |= (1 << 10); in sdhci_pci_o2_fujin2_pci_init()
80 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
83 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
86 scratch_32 |= (1 << 4); in sdhci_pci_o2_fujin2_pci_init()
87 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
93 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
96 scratch_32 &= ~(3 << 12); in sdhci_pci_o2_fujin2_pci_init()
97 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
100 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
103 scratch_32 &= ~(0x01FE); in sdhci_pci_o2_fujin2_pci_init()
104 scratch_32 |= 0x00CC; in sdhci_pci_o2_fujin2_pci_init()
105 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
108 O2_SD_TUNING_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
111 scratch_32 &= ~(0x000000FF); in sdhci_pci_o2_fujin2_pci_init()
112 scratch_32 |= 0x00000066; in sdhci_pci_o2_fujin2_pci_init()
113 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
117 O2_SD_UHS2_L1_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
120 scratch_32 &= ~(0x000000FC); in sdhci_pci_o2_fujin2_pci_init()
121 scratch_32 |= 0x00000084; in sdhci_pci_o2_fujin2_pci_init()
122 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
125 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
128 scratch_32 &= ~((1 << 21) | (1 << 30)); in sdhci_pci_o2_fujin2_pci_init()
130 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
133 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
136 scratch_32 &= ~(0xf0000000); in sdhci_pci_o2_fujin2_pci_init()
137 scratch_32 |= 0x30000000; in sdhci_pci_o2_fujin2_pci_init()
138 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
141 O2_SD_MISC_CTRL4, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
144 scratch_32 &= ~(0x000f0000); in sdhci_pci_o2_fujin2_pci_init()
145 scratch_32 |= 0x00080000; in sdhci_pci_o2_fujin2_pci_init()
146 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
188 u32 scratch_32; in sdhci_pci_o2_probe() local
260 &scratch_32); in sdhci_pci_o2_probe()
261 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); in sdhci_pci_o2_probe()
264 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { in sdhci_pci_o2_probe()
265 scratch_32 = 0x2c280000; in sdhci_pci_o2_probe()
268 o2_pci_set_baseclk(chip, scratch_32); in sdhci_pci_o2_probe()
271 &scratch_32); in sdhci_pci_o2_probe()
274 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; in sdhci_pci_o2_probe()
277 scratch_32); in sdhci_pci_o2_probe()
292 O2_SD_CLK_SETTING, &scratch_32); in sdhci_pci_o2_probe()
296 scratch_32 &= ~(0xFF00); in sdhci_pci_o2_probe()
297 scratch_32 |= 0x07E0C800; in sdhci_pci_o2_probe()
299 O2_SD_CLK_SETTING, scratch_32); in sdhci_pci_o2_probe()
302 O2_SD_CLKREQ, &scratch_32); in sdhci_pci_o2_probe()
305 scratch_32 |= 0x3; in sdhci_pci_o2_probe()
306 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); in sdhci_pci_o2_probe()
309 O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_probe()
313 scratch_32 &= ~(0x1F3F070E); in sdhci_pci_o2_probe()
314 scratch_32 |= 0x18270106; in sdhci_pci_o2_probe()
316 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
320 O2_SD_CAP_REG2, &scratch_32); in sdhci_pci_o2_probe()
323 scratch_32 &= ~(0xE0); in sdhci_pci_o2_probe()
325 O2_SD_CAP_REG2, scratch_32); in sdhci_pci_o2_probe()
350 O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_probe()
352 if ((scratch_32 & 0xff000000) == 0x01000000) { in sdhci_pci_o2_probe()
353 scratch_32 &= 0x0000FFFF; in sdhci_pci_o2_probe()
354 scratch_32 |= 0x1F340000; in sdhci_pci_o2_probe()
357 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
359 scratch_32 &= 0x0000FFFF; in sdhci_pci_o2_probe()
360 scratch_32 |= 0x2c280000; in sdhci_pci_o2_probe()
363 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
367 &scratch_32); in sdhci_pci_o2_probe()
368 scratch_32 |= (1 << 22); in sdhci_pci_o2_probe()
370 O2_SD_FUNC_REG4, scratch_32); in sdhci_pci_o2_probe()