27 static u32 esdhc_readl(struct sdhci_host *host, int reg)  in esdhc_readl()  argument
31 	ret = in_be32(host->ioaddr + reg);  in esdhc_readl()
43 		u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);  in esdhc_readl()
52 static u16 esdhc_readw(struct sdhci_host *host, int reg)  in esdhc_readw()  argument
59 		ret = in_be32(host->ioaddr + base) & 0xffff;  in esdhc_readw()
61 		ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;  in esdhc_readw()
65 static u8 esdhc_readb(struct sdhci_host *host, int reg)  in esdhc_readb()  argument
69 	u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;  in esdhc_readb()
78 		dma_bits = in_be32(host->ioaddr + reg);  in esdhc_readb()
90 static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)  in esdhc_writel()  argument
99 	sdhci_be32bs_writel(host, val, reg);  in esdhc_writel()
102 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)  in esdhc_writew()  argument
112 	sdhci_be32bs_writew(host, val, reg);  in esdhc_writew()
115 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)  in esdhc_writeb()  argument
128 		if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)  in esdhc_writeb()
133 		clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,  in esdhc_writeb()
136 		val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;  in esdhc_writeb()
142 	sdhci_be32bs_writeb(host, val, reg);  in esdhc_writeb()
152 static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)  in esdhci_of_adma_workaround()  argument
159 	tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);  in esdhci_of_adma_workaround()
168 	host->data->error = 0;  in esdhci_of_adma_workaround()
169 	dmastart = sg_dma_address(host->data->sg);  in esdhci_of_adma_workaround()
170 	dmanow = dmastart + host->data->bytes_xfered;  in esdhci_of_adma_workaround()
176 	host->data->bytes_xfered = dmanow - dmastart;  in esdhci_of_adma_workaround()
177 	sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);  in esdhci_of_adma_workaround()
180 static int esdhc_of_enable_dma(struct sdhci_host *host)  in esdhc_of_enable_dma()  argument
182 	setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);  in esdhc_of_enable_dma()
186 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)  in esdhc_of_get_max_clock()  argument
188 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);  in esdhc_of_get_max_clock()
193 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)  in esdhc_of_get_min_clock()  argument
195 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);  in esdhc_of_get_min_clock()
200 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)  in esdhc_of_set_clock()  argument
206 	host->mmc->actual_clock = 0;  in esdhc_of_set_clock()
219 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);  in esdhc_of_set_clock()
222 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);  in esdhc_of_set_clock()
224 	while (host->max_clk / pre_div / 16 > clock && pre_div < 256)  in esdhc_of_set_clock()
227 	while (host->max_clk / pre_div / div > clock && div < 16)  in esdhc_of_set_clock()
230 	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",  in esdhc_of_set_clock()
231 		clock, host->max_clk / pre_div / div);  in esdhc_of_set_clock()
236 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);  in esdhc_of_set_clock()
240 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);  in esdhc_of_set_clock()
244 static void esdhc_of_platform_init(struct sdhci_host *host)  in esdhc_of_platform_init()  argument
248 	vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);  in esdhc_of_platform_init()
251 		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;  in esdhc_of_platform_init()
254 		host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;  in esdhc_of_platform_init()
257 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)  in esdhc_pltfm_set_bus_width()  argument
275 	clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,  in esdhc_pltfm_set_bus_width()
279 static void esdhc_reset(struct sdhci_host *host, u8 mask)  in esdhc_reset()  argument
281 	sdhci_reset(host, mask);  in esdhc_reset()
283 	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);  in esdhc_reset()
284 	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);  in esdhc_reset()
310 	struct sdhci_host *host = dev_get_drvdata(dev);  in esdhc_of_suspend()  local
312 	esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);  in esdhc_of_suspend()
314 	return sdhci_suspend_host(host);  in esdhc_of_suspend()
319 	struct sdhci_host *host = dev_get_drvdata(dev);  in esdhc_of_resume()  local
320 	int ret = sdhci_resume_host(host);  in esdhc_of_resume()
324 		esdhc_of_enable_dma(host);  in esdhc_of_resume()
325 		sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);  in esdhc_of_resume()
353 	struct sdhci_host *host;  in sdhci_esdhc_probe()  local
357 	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata, 0);  in sdhci_esdhc_probe()
358 	if (IS_ERR(host))  in sdhci_esdhc_probe()
359 		return PTR_ERR(host);  in sdhci_esdhc_probe()
369 		host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;  in sdhci_esdhc_probe()
373 	ret = mmc_of_parse(host->mmc);  in sdhci_esdhc_probe()
377 	mmc_of_parse_voltage(np, &host->ocr_mask);  in sdhci_esdhc_probe()
379 	ret = sdhci_add_host(host);  in sdhci_esdhc_probe()