275 		clk_en_a = mci_readl(host, CLKENA);  in dw_mci_prepare_command()
357 		while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {  in dw_mci_wait_while_busy()
424 	u32 bmod = mci_readl(host, BMOD);  in dw_mci_idmac_reset()
435 	temp = mci_readl(host, CTRL);  in dw_mci_idmac_stop_dma()
441 	temp = mci_readl(host, BMOD);  in dw_mci_idmac_stop_dma()
574 	temp = mci_readl(host, CTRL);  in dw_mci_idmac_start_dma()
581 	temp = mci_readl(host, BMOD);  in dw_mci_idmac_start_dma()
860 	temp = mci_readl(host, CTRL);  in dw_mci_submit_data_dma()
866 	temp = mci_readl(host, INTMASK);  in dw_mci_submit_data_dma()
909 		temp = mci_readl(host, INTMASK);  in dw_mci_submit_data()
914 		temp = mci_readl(host, CTRL);  in dw_mci_submit_data()
947 		cmd_status = mci_readl(host, CMD);  in mci_send_cmd()
1169 	regs = mci_readl(slot->host, UHS_REG);  in dw_mci_set_ios()
1203 		regs = mci_readl(slot->host, PWREN);  in dw_mci_set_ios()
1242 		regs = mci_readl(slot->host, PWREN);  in dw_mci_set_ios()
1263 	status = mci_readl(slot->host, STATUS);  in dw_mci_card_busy()
1282 	uhs = mci_readl(host, UHS_REG);  in dw_mci_switch_voltage()
1321 			mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;  in dw_mci_get_ro()
1344 		present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))  in dw_mci_get_cd()
1375 		clk_en_a_old = mci_readl(host, CLKENA);  in dw_mci_init_card()
1404 	int_mask = mci_readl(host, INTMASK);  in dw_mci_enable_sdio_irq()
1495 			cmd->resp[3] = mci_readl(host, RESP0);  in dw_mci_command_complete()
1496 			cmd->resp[2] = mci_readl(host, RESP1);  in dw_mci_command_complete()
1497 			cmd->resp[1] = mci_readl(host, RESP2);  in dw_mci_command_complete()
1498 			cmd->resp[0] = mci_readl(host, RESP3);  in dw_mci_command_complete()
1500 			cmd->resp[0] = mci_readl(host, RESP0);  in dw_mci_command_complete()
2071 			fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))  in dw_mci_read_data_pio()
2083 		status = mci_readl(host, MINTSTS);  in dw_mci_read_data_pio()
2087 		 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));  in dw_mci_read_data_pio()
2127 				 SDMMC_GET_FCNT(mci_readl(host, STATUS)))  in dw_mci_write_data_pio()
2139 		status = mci_readl(host, MINTSTS);  in dw_mci_write_data_pio()
2192 	pending = mci_readl(host, MINTSTS); /* read-only mask reg */  in dw_mci_interrupt()
2200 		    ((mci_readl(host, STATUS) >> 17) & 0x1fff))  in dw_mci_interrupt()
2294 		pending = mci_readl(host, IDSTS64);  in dw_mci_interrupt()
2302 		pending = mci_readl(host, IDSTS);  in dw_mci_interrupt()
2486 	addr_config = (mci_readl(host, HCON) >> 27) & 0x01;  in dw_mci_init_dma()
2544 	ctrl = mci_readl(host, CTRL);  in dw_mci_ctrl_reset()
2550 		ctrl = mci_readl(host, CTRL);  in dw_mci_ctrl_reset()
2591 				status = mci_readl(host, STATUS);  in dw_mci_reset()
2610 		if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {  in dw_mci_reset()
2736 	temp = mci_readl(host, INTMASK);  in dw_mci_enable_cd()
2833 	i = (mci_readl(host, HCON) >> 7) & 0x7;  in dw_mci_probe()
2880 		fifo_size = mci_readl(host, FIFOTH);  in dw_mci_probe()
2898 	host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));  in dw_mci_probe()
2915 		host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;  in dw_mci_probe()