32 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)			\  argument
34 		pci_read_config_word(dev, vsec + 0x6, dest);	\
35 		*dest >>= 4;					\
37 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \  argument
38 	pci_read_config_byte(dev, vsec + 0x8, dest)
40 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \  argument
41 	pci_read_config_byte(dev, vsec + 0x9, dest)
53 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \  argument
54 	pci_read_config_byte(dev, vsec + 0xa, dest)
63 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \  argument
64 	pci_read_config_word(dev, vsec + 0xc, dest)
65 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \  argument
66 	pci_read_config_byte(dev, vsec + 0xe, dest)
67 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \  argument
68 	pci_read_config_byte(dev, vsec + 0xf, dest)
69 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \  argument
70 	pci_read_config_word(dev, vsec + 0x10, dest)
72 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \  argument
73 	pci_read_config_byte(dev, vsec + 0x13, dest)
80 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \  argument
81 	pci_read_config_dword(dev, vsec + 0x20, dest)
82 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \  argument
83 	pci_read_config_dword(dev, vsec + 0x24, dest)
84 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \  argument
85 	pci_read_config_dword(dev, vsec + 0x28, dest)
86 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \  argument
87 	pci_read_config_dword(dev, vsec + 0x2c, dest)