689 	writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));  in prcmu_set_rc_a2p()
795 	writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));  in db8500_prcmu_set_power_state()
796 	writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));  in db8500_prcmu_set_power_state()
797 	writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));  in db8500_prcmu_set_power_state()
798 	writeb((keep_ulp_clk ? 1 : 0),  in db8500_prcmu_set_power_state()
800 	writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));  in db8500_prcmu_set_power_state()
839 		writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));  in config_wakeups()
908 	writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));  in db8500_prcmu_set_arm_opp()
909 	writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));  in db8500_prcmu_set_arm_opp()
910 	writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));  in db8500_prcmu_set_arm_opp()
958 		writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);  in db8500_prcmu_set_ddr_opp()
1034 	writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));  in db8500_prcmu_set_ape_opp()
1035 	writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));  in db8500_prcmu_set_ape_opp()
1036 	writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),  in db8500_prcmu_set_ape_opp()
1099 	writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));  in db8500_prcmu_request_ape_opp_100_voltage()
1128 	writeb(MB1H_RELEASE_USB_WAKEUP,  in prcmu_release_usb_wakeup_state()
1159 	writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));  in request_pll()
1160 	writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));  in request_pll()
1213 		writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));  in db8500_prcmu_set_epod()
1214 	writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));  in db8500_prcmu_set_epod()
1216 	writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));  in db8500_prcmu_set_epod()
1308 	writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));  in request_sysclk()
1310 	writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));  in request_sysclk()
1998 	writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));  in db8500_prcmu_config_esram0_deep_sleep()
1999 	writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),  in db8500_prcmu_config_esram0_deep_sleep()
2001 	writeb(DDR_PWR_STATE_ON,  in db8500_prcmu_config_esram0_deep_sleep()
2003 	writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));  in db8500_prcmu_config_esram0_deep_sleep()
2020 	writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));  in db8500_prcmu_config_hotdog()
2021 	writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));  in db8500_prcmu_config_hotdog()
2038 	writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));  in db8500_prcmu_config_hotmon()
2039 	writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));  in db8500_prcmu_config_hotmon()
2040 	writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),  in db8500_prcmu_config_hotmon()
2042 	writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));  in db8500_prcmu_config_hotmon()
2060 	writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));  in config_hot_period()
2091 	writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));  in prcmu_a9wdog()
2092 	writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));  in prcmu_a9wdog()
2093 	writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));  in prcmu_a9wdog()
2094 	writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));  in prcmu_a9wdog()
2096 	writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));  in prcmu_a9wdog()
2174 	writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));  in prcmu_abb_read()
2175 	writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));  in prcmu_abb_read()
2176 	writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));  in prcmu_abb_read()
2177 	writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));  in prcmu_abb_read()
2178 	writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));  in prcmu_abb_read()
2224 	writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));  in prcmu_abb_write_masked()
2225 	writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));  in prcmu_abb_write_masked()
2226 	writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));  in prcmu_abb_write_masked()
2227 	writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));  in prcmu_abb_write_masked()
2228 	writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));  in prcmu_abb_write_masked()
2370 	writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));  in db8500_prcmu_modem_reset()
2391 	writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));  in ack_dbb_wakeup()