Lines Matching refs:divsel
504 u32 divsel; member
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1446 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1600 u32 divsel; in dsiclk_rate() local
1603 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()
1604 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1606 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()
1607 divsel = dsiclk[n].divsel; in dsiclk_rate()
1609 dsiclk[n].divsel = divsel; in dsiclk_rate()
1611 switch (divsel) { in dsiclk_rate()
1950 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : in set_dsiclk_rate()
1956 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); in set_dsiclk_rate()