575 	u32 zq = 0, val = 0;  in get_zq_config_reg()  local
578 	zq |= val << ZQ_REFINTERVAL_SHIFT;  in get_zq_config_reg()
581 	zq |= val << ZQ_ZQCL_MULT_SHIFT;  in get_zq_config_reg()
584 	zq |= val << ZQ_ZQINIT_MULT_SHIFT;  in get_zq_config_reg()
586 	zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;  in get_zq_config_reg()
589 		zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;  in get_zq_config_reg()
591 		zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;  in get_zq_config_reg()
593 	zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */  in get_zq_config_reg()
596 	zq |= val << ZQ_CS1EN_SHIFT;  in get_zq_config_reg()
598 	return zq;  in get_zq_config_reg()
1138 	u32				pwr_mgmt_ctrl, zq, temp_alert_cfg;  in emif_onetime_settings()  local
1157 	zq = get_zq_config_reg(addressing, device_info->cs1_used,  in emif_onetime_settings()
1159 	writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);  in emif_onetime_settings()