217 	u8 r12, r15, r17, r18, r3D, r82, r84, r89;  in mxl111sf_config_pin_mux_modes()  local
243 	ret = mxl111sf_read_reg(state, 0x3D, &r3D);  in mxl111sf_config_pin_mux_modes()
256 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
262 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
284 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
290 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
312 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
318 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
340 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
346 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
368 		r3D |= PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
374 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
396 		r3D |= PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
402 		r3D |= PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
424 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
430 		r3D |= PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
452 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
458 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
480 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
486 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
509 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
515 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
552 	ret = mxl111sf_write_reg(state, 0x3D, r3D);  in mxl111sf_config_pin_mux_modes()