Lines Matching defs:mxl5005s_state
242 struct mxl5005s_state { struct
243 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
244 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
245 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
246 u32 IF_OUT; /* Desired IF Out Frequency */
247 u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
248 u32 RF_IN; /* RF Input Frequency */
249 u32 Fxtal; /* XTAL Frequency */
250 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
251 u16 TOP; /* Value: take over point */
252 u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */
253 u8 DIV_OUT; /* 4MHz or 16MHz */
254 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
255 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
259 u8 Mod_Type;
263 u8 TF_Type;
266 u32 RF_LO; /* Synth RF LO Frequency */
267 u32 IF_LO; /* Synth IF LO Frequency */
268 u32 TG_LO; /* Synth TG_LO Frequency */
271 u16 Init_Ctrl_Num; /* Number of INIT Control Names */
273 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
275 u16 CH_Ctrl_Num; /* Number of CH Control Names */
277 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
279 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
281 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
284 u16 TunerRegs_Num; /* Number of Tuner Registers */
286 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
289 struct mxl5005s_config *config;
290 struct dvb_frontend *frontend;
291 struct i2c_adapter *i2c;
294 u32 current_mode;