134 	pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);  in cir_dump_regs()
135 	pr_info(" * CR CIR ACTIVE :   0x%x\n",  in cir_dump_regs()
137 	pr_info(" * CR CIR BASE ADDR: 0x%x\n",  in cir_dump_regs()
140 	pr_info(" * CR CIR IRQ NUM:   0x%x\n",  in cir_dump_regs()
145 	pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);  in cir_dump_regs()
146 	pr_info(" * IRCON:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));  in cir_dump_regs()
147 	pr_info(" * IRSTS:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));  in cir_dump_regs()
148 	pr_info(" * IREN:      0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));  in cir_dump_regs()
149 	pr_info(" * RXFCONT:   0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));  in cir_dump_regs()
150 	pr_info(" * CP:        0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));  in cir_dump_regs()
151 	pr_info(" * CC:        0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));  in cir_dump_regs()
152 	pr_info(" * SLCH:      0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));  in cir_dump_regs()
153 	pr_info(" * SLCL:      0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));  in cir_dump_regs()
154 	pr_info(" * FIFOCON:   0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));  in cir_dump_regs()
155 	pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));  in cir_dump_regs()
156 	pr_info(" * SRXFIFO:   0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));  in cir_dump_regs()
157 	pr_info(" * TXFCONT:   0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));  in cir_dump_regs()
158 	pr_info(" * STXFIFO:   0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));  in cir_dump_regs()
159 	pr_info(" * FCCH:      0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));  in cir_dump_regs()
160 	pr_info(" * FCCL:      0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));  in cir_dump_regs()
161 	pr_info(" * IRFSM:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));  in cir_dump_regs()
172 	pr_info("%s: Dump CIR WAKE logical device registers:\n",  in cir_wake_dump_regs()
174 	pr_info(" * CR CIR WAKE ACTIVE :   0x%x\n",  in cir_wake_dump_regs()
176 	pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",  in cir_wake_dump_regs()
179 	pr_info(" * CR CIR WAKE IRQ NUM:   0x%x\n",  in cir_wake_dump_regs()
184 	pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);  in cir_wake_dump_regs()
185 	pr_info(" * IRCON:          0x%x\n",  in cir_wake_dump_regs()
187 	pr_info(" * IRSTS:          0x%x\n",  in cir_wake_dump_regs()
189 	pr_info(" * IREN:           0x%x\n",  in cir_wake_dump_regs()
191 	pr_info(" * FIFO CMP DEEP:  0x%x\n",  in cir_wake_dump_regs()
193 	pr_info(" * FIFO CMP TOL:   0x%x\n",  in cir_wake_dump_regs()
195 	pr_info(" * FIFO COUNT:     0x%x\n",  in cir_wake_dump_regs()
197 	pr_info(" * SLCH:           0x%x\n",  in cir_wake_dump_regs()
199 	pr_info(" * SLCL:           0x%x\n",  in cir_wake_dump_regs()
201 	pr_info(" * FIFOCON:        0x%x\n",  in cir_wake_dump_regs()
203 	pr_info(" * SRXFSTS:        0x%x\n",  in cir_wake_dump_regs()
205 	pr_info(" * SAMPLE RX FIFO: 0x%x\n",  in cir_wake_dump_regs()
207 	pr_info(" * WR FIFO DATA:   0x%x\n",  in cir_wake_dump_regs()
209 	pr_info(" * RD FIFO ONLY:   0x%x\n",  in cir_wake_dump_regs()
211 	pr_info(" * RD FIFO ONLY IDX: 0x%x\n",  in cir_wake_dump_regs()
213 	pr_info(" * FIFO IGNORE:    0x%x\n",  in cir_wake_dump_regs()
215 	pr_info(" * IRFSM:          0x%x\n",  in cir_wake_dump_regs()
219 	pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);  in cir_wake_dump_regs()
220 	pr_info("* Contents =");  in cir_wake_dump_regs()