Lines Matching refs:cfg
24 u32 cfg; in fimc_hw_reset() local
26 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
27 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
31 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
32 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
36 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
37 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
76 u32 cfg, flip; in fimc_hw_set_rotation() local
79 cfg = readl(dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
80 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 | in fimc_hw_set_rotation()
90 cfg |= FIMC_REG_CITRGFMT_INROT90; in fimc_hw_set_rotation()
92 cfg |= FIMC_REG_CITRGFMT_OUTROT90; in fimc_hw_set_rotation()
96 cfg |= fimc_hw_get_target_flip(ctx); in fimc_hw_set_rotation()
97 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
109 u32 cfg; in fimc_hw_set_target_format() local
116 cfg = readl(dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
117 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK | in fimc_hw_set_target_format()
122 cfg |= FIMC_REG_CITRGFMT_RGB; in fimc_hw_set_target_format()
125 cfg |= FIMC_REG_CITRGFMT_YCBCR420; in fimc_hw_set_target_format()
129 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P; in fimc_hw_set_target_format()
131 cfg |= FIMC_REG_CITRGFMT_YCBCR422; in fimc_hw_set_target_format()
138 cfg |= (frame->height << 16) | frame->width; in fimc_hw_set_target_format()
140 cfg |= (frame->width << 16) | frame->height; in fimc_hw_set_target_format()
142 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
144 cfg = readl(dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
145 cfg &= ~FIMC_REG_CITAREA_MASK; in fimc_hw_set_target_format()
146 cfg |= (frame->width * frame->height); in fimc_hw_set_target_format()
147 writel(cfg, dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
154 u32 cfg; in fimc_hw_set_out_dma_size() local
156 cfg = (frame->f_height << 16) | frame->f_width; in fimc_hw_set_out_dma_size()
157 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); in fimc_hw_set_out_dma_size()
160 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
162 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709; in fimc_hw_set_out_dma_size()
164 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709; in fimc_hw_set_out_dma_size()
165 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
175 u32 cfg; in fimc_hw_set_out_dma() local
178 cfg = (offset->y_v << 16) | offset->y_h; in fimc_hw_set_out_dma()
179 writel(cfg, dev->regs + FIMC_REG_CIOYOFF); in fimc_hw_set_out_dma()
181 cfg = (offset->cb_v << 16) | offset->cb_h; in fimc_hw_set_out_dma()
182 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF); in fimc_hw_set_out_dma()
184 cfg = (offset->cr_v << 16) | offset->cr_h; in fimc_hw_set_out_dma()
185 writel(cfg, dev->regs + FIMC_REG_CIOCROFF); in fimc_hw_set_out_dma()
190 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_out_dma()
192 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK | in fimc_hw_set_out_dma()
198 cfg |= ctx->out_order_1p; in fimc_hw_set_out_dma()
200 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE; in fimc_hw_set_out_dma()
202 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE; in fimc_hw_set_out_dma()
205 cfg |= FIMC_REG_CIOCTRL_RGB565; in fimc_hw_set_out_dma()
207 cfg |= FIMC_REG_CIOCTRL_ARGB1555; in fimc_hw_set_out_dma()
209 cfg |= FIMC_REG_CIOCTRL_ARGB4444; in fimc_hw_set_out_dma()
211 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_out_dma()
216 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE); in fimc_hw_en_autoload() local
218 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; in fimc_hw_en_autoload()
220 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; in fimc_hw_en_autoload()
221 writel(cfg, dev->regs + FIMC_REG_ORGISIZE); in fimc_hw_en_autoload()
226 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_en_lastirq() local
228 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE; in fimc_hw_en_lastirq()
230 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE; in fimc_hw_en_lastirq()
231 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_en_lastirq()
238 u32 cfg, shfactor; in fimc_hw_set_prescaler() local
241 cfg = shfactor << 28; in fimc_hw_set_prescaler()
243 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio; in fimc_hw_set_prescaler()
244 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO); in fimc_hw_set_prescaler()
246 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height; in fimc_hw_set_prescaler()
247 writel(cfg, dev->regs + FIMC_REG_CISCPREDST); in fimc_hw_set_prescaler()
257 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_scaler() local
259 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE | in fimc_hw_set_scaler()
266 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE | in fimc_hw_set_scaler()
270 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS; in fimc_hw_set_scaler()
273 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H; in fimc_hw_set_scaler()
276 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V; in fimc_hw_set_scaler()
279 cfg |= FIMC_REG_CISCCTRL_ONE2ONE; in fimc_hw_set_scaler()
284 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565; in fimc_hw_set_scaler()
287 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666; in fimc_hw_set_scaler()
290 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888; in fimc_hw_set_scaler()
299 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565; in fimc_hw_set_scaler()
301 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666; in fimc_hw_set_scaler()
303 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; in fimc_hw_set_scaler()
305 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; in fimc_hw_set_scaler()
308 cfg |= FIMC_REG_CISCCTRL_INTERLACE; in fimc_hw_set_scaler()
311 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_scaler()
319 u32 cfg; in fimc_hw_set_mainscaler() local
326 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_mainscaler()
327 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK | in fimc_hw_set_mainscaler()
331 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio); in fimc_hw_set_mainscaler()
332 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio); in fimc_hw_set_mainscaler()
333 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_mainscaler()
335 cfg = readl(dev->regs + FIMC_REG_CIEXTEN); in fimc_hw_set_mainscaler()
337 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK | in fimc_hw_set_mainscaler()
339 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio); in fimc_hw_set_mainscaler()
340 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio); in fimc_hw_set_mainscaler()
341 writel(cfg, dev->regs + FIMC_REG_CIEXTEN); in fimc_hw_set_mainscaler()
343 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio); in fimc_hw_set_mainscaler()
344 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio); in fimc_hw_set_mainscaler()
345 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_mainscaler()
352 u32 cfg; in fimc_hw_enable_capture() local
354 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_enable_capture()
355 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE; in fimc_hw_enable_capture()
358 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC; in fimc_hw_enable_capture()
360 cfg &= FIMC_REG_CIIMGCPT_IMGCPTEN_SC; in fimc_hw_enable_capture()
362 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN; in fimc_hw_enable_capture()
363 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_enable_capture()
368 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_disable_capture() local
369 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN | in fimc_hw_disable_capture()
371 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_disable_capture()
378 u32 cfg = 0; in fimc_hw_set_effect() local
381 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER | in fimc_hw_set_effect()
383 cfg |= effect->type; in fimc_hw_set_effect()
385 cfg |= (effect->pat_cb << 13) | effect->pat_cr; in fimc_hw_set_effect()
388 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF); in fimc_hw_set_effect()
395 u32 cfg; in fimc_hw_set_rgb_alpha() local
400 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_rgb_alpha()
401 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK; in fimc_hw_set_rgb_alpha()
402 cfg |= (frame->alpha << 4); in fimc_hw_set_rgb_alpha()
403 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_rgb_alpha()
428 u32 cfg; in fimc_hw_set_in_dma() local
431 cfg = (offset->y_v << 16) | offset->y_h; in fimc_hw_set_in_dma()
432 writel(cfg, dev->regs + FIMC_REG_CIIYOFF); in fimc_hw_set_in_dma()
434 cfg = (offset->cb_v << 16) | offset->cb_h; in fimc_hw_set_in_dma()
435 writel(cfg, dev->regs + FIMC_REG_CIICBOFF); in fimc_hw_set_in_dma()
437 cfg = (offset->cr_v << 16) | offset->cr_h; in fimc_hw_set_in_dma()
438 writel(cfg, dev->regs + FIMC_REG_CIICROFF); in fimc_hw_set_in_dma()
447 cfg = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_in_dma()
448 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK in fimc_hw_set_in_dma()
455 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4) in fimc_hw_set_in_dma()
461 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB; in fimc_hw_set_in_dma()
464 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420; in fimc_hw_set_in_dma()
467 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE; in fimc_hw_set_in_dma()
469 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; in fimc_hw_set_in_dma()
474 cfg |= ctx->in_order_1p in fimc_hw_set_in_dma()
477 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422; in fimc_hw_set_in_dma()
480 cfg |= ctx->in_order_2p in fimc_hw_set_in_dma()
483 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; in fimc_hw_set_in_dma()
490 writel(cfg, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_in_dma()
493 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM); in fimc_hw_set_in_dma()
494 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK; in fimc_hw_set_in_dma()
497 cfg |= FIMC_REG_CIDMAPARAM_R_64X32; in fimc_hw_set_in_dma()
500 cfg |= FIMC_REG_CIDMAPARAM_W_64X32; in fimc_hw_set_in_dma()
502 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM); in fimc_hw_set_in_dma()
510 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_input_path() local
511 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK; in fimc_hw_set_input_path()
514 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY; in fimc_hw_set_input_path()
516 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM; in fimc_hw_set_input_path()
518 writel(cfg, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_input_path()
525 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_output_path() local
526 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; in fimc_hw_set_output_path()
528 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; in fimc_hw_set_output_path()
529 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_output_path()
534 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_input_addr() local
535 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS; in fimc_hw_set_input_addr()
536 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_input_addr()
542 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS; in fimc_hw_set_input_addr()
543 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_input_addr()
562 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_polarity() local
564 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC | in fimc_hw_set_camera_polarity()
569 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK; in fimc_hw_set_camera_polarity()
572 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC; in fimc_hw_set_camera_polarity()
575 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF; in fimc_hw_set_camera_polarity()
578 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC; in fimc_hw_set_camera_polarity()
581 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD; in fimc_hw_set_camera_polarity()
583 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_polarity()
606 u32 bus_width, cfg = 0; in fimc_hw_set_camera_source() local
614 cfg = pix_desc[i].cisrcfmt; in fimc_hw_set_camera_source()
629 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_set_camera_source()
631 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT; in fimc_hw_set_camera_source()
636 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_set_camera_source()
644 cfg |= (f->o_width << 16) | f->o_height; in fimc_hw_set_camera_source()
645 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT); in fimc_hw_set_camera_source()
653 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST); in fimc_hw_set_camera_offset() local
655 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK); in fimc_hw_set_camera_offset()
656 cfg |= FIMC_REG_CIWDOFST_OFF_EN | in fimc_hw_set_camera_offset()
659 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST); in fimc_hw_set_camera_offset()
664 cfg = (hoff2 << 16) | voff2; in fimc_hw_set_camera_offset()
665 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2); in fimc_hw_set_camera_offset()
673 u32 cfg, tmp; in fimc_hw_set_camera_type() local
675 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_type()
678 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A | in fimc_hw_set_camera_type()
685 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI; in fimc_hw_set_camera_type()
688 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A; in fimc_hw_set_camera_type()
698 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG; in fimc_hw_set_camera_type()
712 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A; in fimc_hw_set_camera_type()
715 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB; in fimc_hw_set_camera_type()
719 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB; in fimc_hw_set_camera_type()
729 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_type()
736 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_clear_irq() local
737 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR; in fimc_hw_clear_irq()
738 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_clear_irq()
743 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_enable_scaler() local
745 cfg |= FIMC_REG_CISCCTRL_SCALERSTART; in fimc_hw_enable_scaler()
747 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART; in fimc_hw_enable_scaler()
748 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_enable_scaler()
753 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_activate_input_dma() local
755 cfg |= FIMC_REG_MSCTRL_ENVID; in fimc_hw_activate_input_dma()
757 cfg &= ~FIMC_REG_MSCTRL_ENVID; in fimc_hw_activate_input_dma()
758 writel(cfg, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_activate_input_dma()