28 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
30 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
33 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
40 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
45 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
47 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
52 	u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_get_interrupt_source()
59 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
61 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
80 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
83 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
88 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
90 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
95 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
97 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
106 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
111 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
147 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
150 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
152 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
157 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
166 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
170 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
176 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);  in flite_hw_set_window_offset()
182 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
187 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
194 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
215 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
222 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
229 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
240 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
247 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
255 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
258 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
261 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
264 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
278 		writel(buf->paddr, dev->regs + FLITE_REG_CIOSA);  in flite_hw_set_dma_buffer()
280 		writel(buf->paddr, dev->regs + FLITE_REG_CIOSAN(index - 1));  in flite_hw_set_dma_buffer()
282 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
284 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
294 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
296 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
303 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
307 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
312 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
345 		u32 cfg = readl(dev->regs + registers[i].offset);  in flite_hw_dump_regs()