129 static struct vpss_oper_config oper_cfg;  variable
134 	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);  in bl_regr()
139 	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);  in bl_regw()
144 	return __raw_readl(oper_cfg.vpss_regs_base1 + offset);  in vpss_regr()
149 	__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);  in vpss_regw()
155 	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);  in isp5_read()
161 	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);  in isp5_write()
183 	if (!oper_cfg.hw_ops.dma_complete_interrupt)  in vpss_dma_complete_interrupt()
185 	return oper_cfg.hw_ops.dma_complete_interrupt();  in vpss_dma_complete_interrupt()
191 	if (!oper_cfg.hw_ops.select_ccdc_source)  in vpss_select_ccdc_source()
194 	oper_cfg.hw_ops.select_ccdc_source(src_sel);  in vpss_select_ccdc_source()
216 	if (!oper_cfg.hw_ops.set_sync_pol)  in vpss_set_sync_pol()
219 	oper_cfg.hw_ops.set_sync_pol(sync);  in vpss_set_sync_pol()
225 	if (!oper_cfg.hw_ops.clear_wbl_overflow)  in vpss_clear_wbl_overflow()
228 	return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);  in vpss_clear_wbl_overflow()
269 	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);  in dm355_enable_clock()
277 	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);  in dm355_enable_clock()
353 	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);  in dm365_enable_clock()
362 	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);  in dm365_enable_clock()
369 	if (!oper_cfg.hw_ops.enable_clock)  in vpss_enable_clock()
372 	return oper_cfg.hw_ops.enable_clock(clock_sel, en);  in vpss_enable_clock()
390 	if (!oper_cfg.hw_ops.set_pg_frame_size)  in vpss_set_pg_frame_size()
393 	oper_cfg.hw_ops.set_pg_frame_size(frame_size);  in vpss_set_pg_frame_size()
418 		oper_cfg.platform = DM355;  in vpss_probe()
420 		oper_cfg.platform = DM365;  in vpss_probe()
422 		oper_cfg.platform = DM644X;  in vpss_probe()
432 	oper_cfg.vpss_regs_base0 = devm_ioremap_resource(&pdev->dev, res);  in vpss_probe()
433 	if (IS_ERR(oper_cfg.vpss_regs_base0))  in vpss_probe()
434 		return PTR_ERR(oper_cfg.vpss_regs_base0);  in vpss_probe()
436 	if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {  in vpss_probe()
439 		oper_cfg.vpss_regs_base1 = devm_ioremap_resource(&pdev->dev,  in vpss_probe()
441 		if (IS_ERR(oper_cfg.vpss_regs_base1))  in vpss_probe()
442 			return PTR_ERR(oper_cfg.vpss_regs_base1);  in vpss_probe()
445 	if (oper_cfg.platform == DM355) {  in vpss_probe()
446 		oper_cfg.hw_ops.enable_clock = dm355_enable_clock;  in vpss_probe()
447 		oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;  in vpss_probe()
451 	} else if (oper_cfg.platform == DM365) {  in vpss_probe()
452 		oper_cfg.hw_ops.enable_clock = dm365_enable_clock;  in vpss_probe()
453 		oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;  in vpss_probe()
469 		oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;  in vpss_probe()
475 	spin_lock_init(&oper_cfg.vpss_lock);  in vpss_probe()
515 	iounmap(oper_cfg.vpss_regs_base2);  in vpss_exit()
525 	oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);  in vpss_init()
527 		     VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);  in vpss_init()