132 static inline u32 bl_regr(u32 offset)  in bl_regr()  argument
134 	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);  in bl_regr()
137 static inline void bl_regw(u32 val, u32 offset)  in bl_regw()  argument
139 	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);  in bl_regw()
142 static inline u32 vpss_regr(u32 offset)  in vpss_regr()  argument
144 	return __raw_readl(oper_cfg.vpss_regs_base1 + offset);  in vpss_regr()
147 static inline void vpss_regw(u32 val, u32 offset)  in vpss_regw()  argument
149 	__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);  in vpss_regw()
153 static inline u32 isp5_read(u32 offset)  in isp5_read()  argument
155 	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);  in isp5_read()
159 static inline void isp5_write(u32 val, u32 offset)  in isp5_write()  argument
161 	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);  in isp5_write()
284 	u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;  in dm365_enable_clock()  local
285 	u32 (*read)(u32 offset) = isp5_read;  in dm365_enable_clock()
286 	void(*write)(u32 val, u32 offset) = isp5_write;  in dm365_enable_clock()
315 		offset = DM365_VPBE_CLK_CTRL;  in dm365_enable_clock()
321 		offset = DM365_VPBE_CLK_CTRL;  in dm365_enable_clock()
327 		offset = DM365_VPBE_CLK_CTRL;  in dm365_enable_clock()
333 		offset = DM365_VPBE_CLK_CTRL;  in dm365_enable_clock()
339 		offset = DM365_VPBE_CLK_CTRL;  in dm365_enable_clock()
345 		offset = DM365_VPBE_CLK_CTRL;  in dm365_enable_clock()
354 	utemp = read(offset);  in dm365_enable_clock()
361 	write(utemp, offset);  in dm365_enable_clock()