280 				u8 channel_id, u8 config_channel_id)  in vpif_set_mode_info()  argument
287 	regw(value, vpifregs[channel_id].h_cfg);  in vpif_set_mode_info()
292 	regw(value, vpifregs[channel_id].v_cfg_00);  in vpif_set_mode_info()
297 	regw(value, vpifregs[channel_id].v_cfg_01);  in vpif_set_mode_info()
302 	regw(value, vpifregs[channel_id].v_cfg_02);  in vpif_set_mode_info()
305 	regw(value, vpifregs[channel_id].v_cfg);  in vpif_set_mode_info()
314 				u8 channel_id, u8 found)  in config_vpif_params()  argument
321 	start = channel_id;  in config_vpif_params()
322 	end = channel_id + found;  in config_vpif_params()
326 		if (channel_id < 2)  in config_vpif_params()
340 		if (channel_id > 1)	/* Set the Pixel enable bit */  in config_vpif_params()
369 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)  in vpif_set_video_params()  argument
374 	vpif_set_mode_info(config, channel_id, channel_id);  in vpif_set_video_params()
377 		vpif_set_mode_info(config, channel_id + 1, channel_id);  in vpif_set_video_params()
381 	config_vpif_params(vpifparams, channel_id, found);  in vpif_set_video_params()
391 				u8 channel_id)  in vpif_set_vbi_display_params()  argument
397 	regw(value, vpifregs[channel_id].vanc0_strt);  in vpif_set_vbi_display_params()
401 	regw(value, vpifregs[channel_id].vanc1_strt);  in vpif_set_vbi_display_params()
405 	regw(value, vpifregs[channel_id].vanc0_size);  in vpif_set_vbi_display_params()
409 	regw(value, vpifregs[channel_id].vanc1_size);  in vpif_set_vbi_display_params()
414 int vpif_channel_getfid(u8 channel_id)  in vpif_channel_getfid()  argument
416 	return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)  in vpif_channel_getfid()