377 #define dm_writeb(reg, value)	outb((value), (dm_io_mem(reg)))  macro
499 		dm_writeb(DM1105_I2CCTR, 0x00);  in dm1105_i2c_xfer()
504 			dm_writeb(DM1105_I2CDAT, addr);  in dm1105_i2c_xfer()
506 				dm_writeb(DM1105_I2CDAT + byte + 1, 0);  in dm1105_i2c_xfer()
508 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);  in dm1105_i2c_xfer()
530 				dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);  in dm1105_i2c_xfer()
531 				dm_writeb(DM1105_I2CDAT + 1, 0xf7);  in dm1105_i2c_xfer()
534 					dm_writeb(DM1105_I2CDAT + byte + 2, data);  in dm1105_i2c_xfer()
536 				dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));  in dm1105_i2c_xfer()
552 			dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);  in dm1105_i2c_xfer()
555 				dm_writeb(DM1105_I2CDAT + byte + 1, data);  in dm1105_i2c_xfer()
557 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);  in dm1105_i2c_xfer()
639 	dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);  in dm1105_enable_irqs()
640 	dm_writeb(DM1105_CR, 1);  in dm1105_enable_irqs()
645 	dm_writeb(DM1105_INTMAK, INTMAK_IRM);  in dm1105_disable_irqs()
646 	dm_writeb(DM1105_CR, 0);  in dm1105_disable_irqs()
700 			dm_writeb(DM1105_RST, 1);  in dm1105_dmx_buffer()
724 	dm_writeb(DM1105_INTSTS, intsts);  in dm1105_irq()
790 	dm_writeb(DM1105_HOST_CTR, 0);  in dm1105_hw_init()
793 	dm_writeb(DM1105_DTALENTH, 188);  in dm1105_hw_init()
802 	dm_writeb(DM1105_INTCNT, 47);  in dm1105_hw_init()
805 	dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));  in dm1105_hw_init()
806 	dm_writeb(DM1105_IRMODE, 0);  in dm1105_hw_init()
817 	dm_writeb(DM1105_IRCTR, 0);  in dm1105_hw_exit()
818 	dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);  in dm1105_hw_exit()