42 					const struct sram_channel *ch,  in cx25821_sram_channel_setup_upstream()  argument
48 	if (ch->cmds_start == 0) {  in cx25821_sram_channel_setup_upstream()
49 		cx_write(ch->ptr1_reg, 0);  in cx25821_sram_channel_setup_upstream()
50 		cx_write(ch->ptr2_reg, 0);  in cx25821_sram_channel_setup_upstream()
51 		cx_write(ch->cnt2_reg, 0);  in cx25821_sram_channel_setup_upstream()
52 		cx_write(ch->cnt1_reg, 0);  in cx25821_sram_channel_setup_upstream()
57 	cdt = ch->cdt;  in cx25821_sram_channel_setup_upstream()
58 	lines = ch->fifo_size / bpl;  in cx25821_sram_channel_setup_upstream()
67 		cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);  in cx25821_sram_channel_setup_upstream()
74 	cx_write(ch->cmds_start + 0, risc);  in cx25821_sram_channel_setup_upstream()
76 	cx_write(ch->cmds_start + 4, 0);  in cx25821_sram_channel_setup_upstream()
77 	cx_write(ch->cmds_start + 8, cdt);  in cx25821_sram_channel_setup_upstream()
78 	cx_write(ch->cmds_start + 12, (lines * 16) >> 3);  in cx25821_sram_channel_setup_upstream()
79 	cx_write(ch->cmds_start + 16, ch->ctrl_start);  in cx25821_sram_channel_setup_upstream()
81 	cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);  in cx25821_sram_channel_setup_upstream()
84 		cx_write(ch->cmds_start + i, 0);  in cx25821_sram_channel_setup_upstream()
87 	cx_write(ch->ptr1_reg, ch->fifo_start);  in cx25821_sram_channel_setup_upstream()
88 	cx_write(ch->ptr2_reg, cdt);  in cx25821_sram_channel_setup_upstream()
89 	cx_write(ch->cnt2_reg, (lines * 16) >> 3);  in cx25821_sram_channel_setup_upstream()
90 	cx_write(ch->cnt1_reg, (bpl >> 3) - 1);  in cx25821_sram_channel_setup_upstream()
517 				    const struct sram_channel *ch,  in cx25821_set_pixelengine()  argument
531 	cx_write(ch->vid_fmt_ctl, value);  in cx25821_set_pixelengine()
535 	cx_write(ch->vid_active_ctl1, width);  in cx25821_set_pixelengine()
546 	cx_write(ch->vid_active_ctl2, value);  in cx25821_set_pixelengine()
548 	cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);  in cx25821_set_pixelengine()