Lines Matching refs:sdp_io_write
392 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in sdp_io_write() function
401 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); in sdp_io_write_and_or()
838 sdp_io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
1633 sdp_io_write(sd, 0xe1, c->A1); in sdp_csc_coeff()
1635 sdp_io_write(sd, 0xe3, c->A2); in sdp_csc_coeff()
1637 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
1641 sdp_io_write(sd, 0xe7, c->A4); in sdp_csc_coeff()
1645 sdp_io_write(sd, 0xe9, c->B1); in sdp_csc_coeff()
1647 sdp_io_write(sd, 0xeb, c->B2); in sdp_csc_coeff()
1649 sdp_io_write(sd, 0xed, c->B3); in sdp_csc_coeff()
1653 sdp_io_write(sd, 0xef, c->B4); in sdp_csc_coeff()
1657 sdp_io_write(sd, 0xf1, c->C1); in sdp_csc_coeff()
1659 sdp_io_write(sd, 0xf3, c->C2); in sdp_csc_coeff()
1661 sdp_io_write(sd, 0xf5, c->C3); in sdp_csc_coeff()
1665 sdp_io_write(sd, 0xf7, c->C4); in sdp_csc_coeff()
1698 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ in select_input()
1699 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ in select_input()
1711 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ in select_input()
2447 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2448 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); in adv7842_s_sdp_io()
2449 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); in adv7842_s_sdp_io()
2450 sdp_io_write(sd, 0x97, s->hs_width & 0xff); in adv7842_s_sdp_io()
2451 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2452 sdp_io_write(sd, 0x99, s->de_beg & 0xff); in adv7842_s_sdp_io()
2453 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); in adv7842_s_sdp_io()
2454 sdp_io_write(sd, 0x9b, s->de_end & 0xff); in adv7842_s_sdp_io()
2455 sdp_io_write(sd, 0xa8, s->vs_beg_o); in adv7842_s_sdp_io()
2456 sdp_io_write(sd, 0xa9, s->vs_beg_e); in adv7842_s_sdp_io()
2457 sdp_io_write(sd, 0xaa, s->vs_end_o); in adv7842_s_sdp_io()
2458 sdp_io_write(sd, 0xab, s->vs_end_e); in adv7842_s_sdp_io()
2459 sdp_io_write(sd, 0xac, s->de_v_beg_o); in adv7842_s_sdp_io()
2460 sdp_io_write(sd, 0xad, s->de_v_beg_e); in adv7842_s_sdp_io()
2461 sdp_io_write(sd, 0xae, s->de_v_end_o); in adv7842_s_sdp_io()
2462 sdp_io_write(sd, 0xaf, s->de_v_end_e); in adv7842_s_sdp_io()
2465 sdp_io_write(sd, 0x94, 0x00); in adv7842_s_sdp_io()
2466 sdp_io_write(sd, 0x95, 0x00); in adv7842_s_sdp_io()
2467 sdp_io_write(sd, 0x96, 0x00); in adv7842_s_sdp_io()
2468 sdp_io_write(sd, 0x97, 0x20); in adv7842_s_sdp_io()
2469 sdp_io_write(sd, 0x98, 0x00); in adv7842_s_sdp_io()
2470 sdp_io_write(sd, 0x99, 0x00); in adv7842_s_sdp_io()
2471 sdp_io_write(sd, 0x9a, 0x00); in adv7842_s_sdp_io()
2472 sdp_io_write(sd, 0x9b, 0x00); in adv7842_s_sdp_io()
2473 sdp_io_write(sd, 0xa8, 0x04); in adv7842_s_sdp_io()
2474 sdp_io_write(sd, 0xa9, 0x04); in adv7842_s_sdp_io()
2475 sdp_io_write(sd, 0xaa, 0x04); in adv7842_s_sdp_io()
2476 sdp_io_write(sd, 0xab, 0x04); in adv7842_s_sdp_io()
2477 sdp_io_write(sd, 0xac, 0x04); in adv7842_s_sdp_io()
2478 sdp_io_write(sd, 0xad, 0x04); in adv7842_s_sdp_io()
2479 sdp_io_write(sd, 0xae, 0x04); in adv7842_s_sdp_io()
2480 sdp_io_write(sd, 0xaf, 0x04); in adv7842_s_sdp_io()
2592 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ in adv7842_core_init()
2593 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ in adv7842_core_init()
2594 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
2595 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
2596 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
2598 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ in adv7842_core_init()
2599 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ in adv7842_core_init()
2600 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, in adv7842_core_init()
2602 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ in adv7842_core_init()
2603 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
2604 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
2605 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
2612 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ in adv7842_core_init()
2672 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2673 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2674 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2675 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2676 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2677 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2678 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2679 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2680 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2681 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2685 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ in adv7842_ddr_ram_test()