Lines Matching refs:sd
69 struct v4l2_subdev sd; member
214 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) in to_state() argument
216 return container_of(sd, struct adv7842_state, sd); in to_state()
221 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; in to_sd()
319 static inline int io_read(struct v4l2_subdev *sd, u8 reg) in io_read() argument
321 struct i2c_client *client = v4l2_get_subdevdata(sd); in io_read()
326 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in io_write() argument
328 struct i2c_client *client = v4l2_get_subdevdata(sd); in io_write()
333 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in io_write_and_or() argument
335 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); in io_write_and_or()
338 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) in avlink_read() argument
340 struct adv7842_state *state = to_state(sd); in avlink_read()
345 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) in avlink_write() argument
347 struct adv7842_state *state = to_state(sd); in avlink_write()
352 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) in cec_read() argument
354 struct adv7842_state *state = to_state(sd); in cec_read()
359 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) in cec_write() argument
361 struct adv7842_state *state = to_state(sd); in cec_write()
366 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in cec_write_and_or() argument
368 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); in cec_write_and_or()
371 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) in infoframe_read() argument
373 struct adv7842_state *state = to_state(sd); in infoframe_read()
378 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) in infoframe_write() argument
380 struct adv7842_state *state = to_state(sd); in infoframe_write()
385 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) in sdp_io_read() argument
387 struct adv7842_state *state = to_state(sd); in sdp_io_read()
392 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in sdp_io_write() argument
394 struct adv7842_state *state = to_state(sd); in sdp_io_write()
399 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in sdp_io_write_and_or() argument
401 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); in sdp_io_write_and_or()
404 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) in sdp_read() argument
406 struct adv7842_state *state = to_state(sd); in sdp_read()
411 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in sdp_write() argument
413 struct adv7842_state *state = to_state(sd); in sdp_write()
418 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in sdp_write_and_or() argument
420 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); in sdp_write_and_or()
423 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) in afe_read() argument
425 struct adv7842_state *state = to_state(sd); in afe_read()
430 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) in afe_write() argument
432 struct adv7842_state *state = to_state(sd); in afe_write()
437 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in afe_write_and_or() argument
439 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); in afe_write_and_or()
442 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) in rep_read() argument
444 struct adv7842_state *state = to_state(sd); in rep_read()
449 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) in rep_write() argument
451 struct adv7842_state *state = to_state(sd); in rep_write()
456 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in rep_write_and_or() argument
458 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); in rep_write_and_or()
461 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) in edid_read() argument
463 struct adv7842_state *state = to_state(sd); in edid_read()
468 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) in edid_write() argument
470 struct adv7842_state *state = to_state(sd); in edid_write()
475 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) in hdmi_read() argument
477 struct adv7842_state *state = to_state(sd); in hdmi_read()
482 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) in hdmi_write() argument
484 struct adv7842_state *state = to_state(sd); in hdmi_write()
489 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in hdmi_write_and_or() argument
491 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); in hdmi_write_and_or()
494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) in cp_read() argument
496 struct adv7842_state *state = to_state(sd); in cp_read()
501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in cp_write() argument
503 struct adv7842_state *state = to_state(sd); in cp_write()
508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in cp_write_and_or() argument
510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); in cp_write_and_or()
513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) in vdp_read() argument
515 struct adv7842_state *state = to_state(sd); in vdp_read()
520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in vdp_write() argument
522 struct adv7842_state *state = to_state(sd); in vdp_write()
527 static void main_reset(struct v4l2_subdev *sd) in main_reset() argument
529 struct i2c_client *client = v4l2_get_subdevdata(sd); in main_reset()
531 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in main_reset()
540 static inline bool is_analog_input(struct v4l2_subdev *sd) in is_analog_input() argument
542 struct adv7842_state *state = to_state(sd); in is_analog_input()
548 static inline bool is_digital_input(struct v4l2_subdev *sd) in is_digital_input() argument
550 struct adv7842_state *state = to_state(sd); in is_digital_input()
578 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) in adv7842_get_dv_timings_cap() argument
580 return is_digital_input(sd) ? &adv7842_timings_cap_digital : in adv7842_get_dv_timings_cap()
591 struct v4l2_subdev *sd = &state->sd; in adv7842_delayed_work_enable_hotplug() local
595 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", in adv7842_delayed_work_enable_hotplug()
602 io_write_and_or(sd, 0x20, 0xcf, mask); in adv7842_delayed_work_enable_hotplug()
605 static int edid_write_vga_segment(struct v4l2_subdev *sd) in edid_write_vga_segment() argument
607 struct i2c_client *client = v4l2_get_subdevdata(sd); in edid_write_vga_segment()
608 struct adv7842_state *state = to_state(sd); in edid_write_vga_segment()
613 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); in edid_write_vga_segment()
616 io_write_and_or(sd, 0x20, 0xcf, 0x00); in edid_write_vga_segment()
619 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); in edid_write_vga_segment()
622 rep_write_and_or(sd, 0x77, 0xef, 0x10); in edid_write_vga_segment()
633 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); in edid_write_vga_segment()
636 if (rep_read(sd, 0x79) & 0x20) in edid_write_vga_segment()
685 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) in edid_write_hdmi_segment() argument
687 struct i2c_client *client = v4l2_get_subdevdata(sd); in edid_write_hdmi_segment()
688 struct adv7842_state *state = to_state(sd); in edid_write_hdmi_segment()
694 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n", in edid_write_hdmi_segment()
698 io_write_and_or(sd, 0x20, 0xcf, 0x00); in edid_write_hdmi_segment()
701 rep_write_and_or(sd, 0x77, 0xf3, 0x00); in edid_write_hdmi_segment()
707 rep_write_and_or(sd, 0x77, 0xef, 0x00); in edid_write_hdmi_segment()
719 rep_write(sd, 0x72, val[spa_loc]); in edid_write_hdmi_segment()
720 rep_write(sd, 0x73, val[spa_loc + 1]); in edid_write_hdmi_segment()
722 rep_write(sd, 0x74, val[spa_loc]); in edid_write_hdmi_segment()
723 rep_write(sd, 0x75, val[spa_loc + 1]); in edid_write_hdmi_segment()
725 rep_write(sd, 0x76, spa_loc & 0xff); in edid_write_hdmi_segment()
726 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); in edid_write_hdmi_segment()
731 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); in edid_write_hdmi_segment()
734 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) in edid_write_hdmi_segment()
754 static void adv7842_inv_register(struct v4l2_subdev *sd) in adv7842_inv_register() argument
756 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv7842_inv_register()
757 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv7842_inv_register()
758 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv7842_inv_register()
759 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv7842_inv_register()
760 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); in adv7842_inv_register()
761 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); in adv7842_inv_register()
762 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv7842_inv_register()
763 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv7842_inv_register()
764 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv7842_inv_register()
765 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv7842_inv_register()
766 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); in adv7842_inv_register()
767 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); in adv7842_inv_register()
770 static int adv7842_g_register(struct v4l2_subdev *sd, in adv7842_g_register() argument
776 reg->val = io_read(sd, reg->reg & 0xff); in adv7842_g_register()
779 reg->val = avlink_read(sd, reg->reg & 0xff); in adv7842_g_register()
782 reg->val = cec_read(sd, reg->reg & 0xff); in adv7842_g_register()
785 reg->val = infoframe_read(sd, reg->reg & 0xff); in adv7842_g_register()
788 reg->val = sdp_io_read(sd, reg->reg & 0xff); in adv7842_g_register()
791 reg->val = sdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
794 reg->val = afe_read(sd, reg->reg & 0xff); in adv7842_g_register()
797 reg->val = rep_read(sd, reg->reg & 0xff); in adv7842_g_register()
800 reg->val = edid_read(sd, reg->reg & 0xff); in adv7842_g_register()
803 reg->val = hdmi_read(sd, reg->reg & 0xff); in adv7842_g_register()
806 reg->val = cp_read(sd, reg->reg & 0xff); in adv7842_g_register()
809 reg->val = vdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
812 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv7842_g_register()
813 adv7842_inv_register(sd); in adv7842_g_register()
819 static int adv7842_s_register(struct v4l2_subdev *sd, in adv7842_s_register() argument
826 io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
829 avlink_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
832 cec_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
835 infoframe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
838 sdp_io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
841 sdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
844 afe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
847 rep_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
850 edid_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
853 hdmi_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
856 cp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
859 vdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv7842_s_register()
863 adv7842_inv_register(sd); in adv7842_s_register()
870 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) in adv7842_s_detect_tx_5v_ctrl() argument
872 struct adv7842_state *state = to_state(sd); in adv7842_s_detect_tx_5v_ctrl()
874 u8 reg_io_6f = io_read(sd, 0x6f); in adv7842_s_detect_tx_5v_ctrl()
882 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); in adv7842_s_detect_tx_5v_ctrl()
889 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, in find_and_set_predefined_video_timings() argument
898 is_digital_input(sd) ? 250000 : 1000000)) in find_and_set_predefined_video_timings()
901 io_write(sd, 0x00, predef_vid_timings[i].vid_std); in find_and_set_predefined_video_timings()
903 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); in find_and_set_predefined_video_timings()
910 static int configure_predefined_video_timings(struct v4l2_subdev *sd, in configure_predefined_video_timings() argument
913 struct adv7842_state *state = to_state(sd); in configure_predefined_video_timings()
916 v4l2_dbg(1, debug, sd, "%s\n", __func__); in configure_predefined_video_timings()
919 io_write(sd, 0x16, 0x43); in configure_predefined_video_timings()
920 io_write(sd, 0x17, 0x5a); in configure_predefined_video_timings()
922 cp_write_and_or(sd, 0x81, 0xef, 0x00); in configure_predefined_video_timings()
923 cp_write(sd, 0x26, 0x00); in configure_predefined_video_timings()
924 cp_write(sd, 0x27, 0x00); in configure_predefined_video_timings()
925 cp_write(sd, 0x28, 0x00); in configure_predefined_video_timings()
926 cp_write(sd, 0x29, 0x00); in configure_predefined_video_timings()
927 cp_write(sd, 0x8f, 0x40); in configure_predefined_video_timings()
928 cp_write(sd, 0x90, 0x00); in configure_predefined_video_timings()
929 cp_write(sd, 0xa5, 0x00); in configure_predefined_video_timings()
930 cp_write(sd, 0xa6, 0x00); in configure_predefined_video_timings()
931 cp_write(sd, 0xa7, 0x00); in configure_predefined_video_timings()
932 cp_write(sd, 0xab, 0x00); in configure_predefined_video_timings()
933 cp_write(sd, 0xac, 0x00); in configure_predefined_video_timings()
938 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
941 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
945 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
948 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
952 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in configure_predefined_video_timings()
962 static void configure_custom_video_timings(struct v4l2_subdev *sd, in configure_custom_video_timings() argument
965 struct adv7842_state *state = to_state(sd); in configure_custom_video_timings()
966 struct i2c_client *client = v4l2_get_subdevdata(sd); in configure_custom_video_timings()
980 v4l2_dbg(2, debug, sd, "%s\n", __func__); in configure_custom_video_timings()
986 io_write(sd, 0x00, 0x07); /* video std */ in configure_custom_video_timings()
987 io_write(sd, 0x01, 0x02); /* prim mode */ in configure_custom_video_timings()
989 cp_write_and_or(sd, 0x81, 0xef, 0x10); in configure_custom_video_timings()
995 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); in configure_custom_video_timings()
1000 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); in configure_custom_video_timings()
1001 cp_write(sd, 0x27, (cp_start_sav & 0xff)); in configure_custom_video_timings()
1002 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); in configure_custom_video_timings()
1003 cp_write(sd, 0x29, (cp_start_eav & 0xff)); in configure_custom_video_timings()
1006 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); in configure_custom_video_timings()
1007 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | in configure_custom_video_timings()
1009 cp_write(sd, 0xa7, cp_end_vbi & 0xff); in configure_custom_video_timings()
1014 io_write(sd, 0x00, 0x02); /* video std */ in configure_custom_video_timings()
1015 io_write(sd, 0x01, 0x06); /* prim mode */ in configure_custom_video_timings()
1018 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in configure_custom_video_timings()
1023 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); in configure_custom_video_timings()
1024 cp_write(sd, 0x90, ch1_fr_ll & 0xff); in configure_custom_video_timings()
1025 cp_write(sd, 0xab, (height >> 4) & 0xff); in configure_custom_video_timings()
1026 cp_write(sd, 0xac, (height & 0x0f) << 4); in configure_custom_video_timings()
1029 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b… in adv7842_set_offset() argument
1031 struct adv7842_state *state = to_state(sd); in adv7842_set_offset()
1040 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv7842_set_offset()
1044 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); in adv7842_set_offset()
1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); in adv7842_set_offset()
1054 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 ga… in adv7842_set_gain() argument
1056 struct adv7842_state *state = to_state(sd); in adv7842_set_gain()
1069 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv7842_set_gain()
1080 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); in adv7842_set_gain()
1083 static void set_rgb_quantization_range(struct v4l2_subdev *sd) in set_rgb_quantization_range() argument
1085 struct adv7842_state *state = to_state(sd); in set_rgb_quantization_range()
1086 bool rgb_output = io_read(sd, 0x02) & 0x02; in set_rgb_quantization_range()
1087 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in set_rgb_quantization_range()
1089 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", in set_rgb_quantization_range()
1093 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1094 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1101 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1108 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in set_rgb_quantization_range()
1115 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in set_rgb_quantization_range()
1124 io_write_and_or(sd, 0x02, 0x0f, 0x00); in set_rgb_quantization_range()
1127 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1129 if (is_digital_input(sd) && rgb_output) { in set_rgb_quantization_range()
1130 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1132 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1133 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1140 io_write_and_or(sd, 0x02, 0x0f, 0x20); in set_rgb_quantization_range()
1145 io_write_and_or(sd, 0x02, 0x0f, 0x00); in set_rgb_quantization_range()
1151 io_write_and_or(sd, 0x02, 0x0f, 0x60); in set_rgb_quantization_range()
1156 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1158 if (is_analog_input(sd) || hdmi_signal) in set_rgb_quantization_range()
1163 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1165 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1166 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1174 struct v4l2_subdev *sd = to_sd(ctrl); in adv7842_s_ctrl() local
1175 struct adv7842_state *state = to_state(sd); in adv7842_s_ctrl()
1184 cp_write(sd, 0x3c, ctrl->val); in adv7842_s_ctrl()
1185 sdp_write(sd, 0x14, ctrl->val); in adv7842_s_ctrl()
1189 cp_write(sd, 0x3a, ctrl->val); in adv7842_s_ctrl()
1190 sdp_write(sd, 0x13, ctrl->val); in adv7842_s_ctrl()
1194 cp_write(sd, 0x3b, ctrl->val); in adv7842_s_ctrl()
1195 sdp_write(sd, 0x15, ctrl->val); in adv7842_s_ctrl()
1199 cp_write(sd, 0x3d, ctrl->val); in adv7842_s_ctrl()
1200 sdp_write(sd, 0x16, ctrl->val); in adv7842_s_ctrl()
1205 afe_write(sd, 0xc8, ctrl->val); in adv7842_s_ctrl()
1208 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1209 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1229 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); in adv7842_s_ctrl()
1230 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); in adv7842_s_ctrl()
1233 cp_write(sd, 0xc1, R); in adv7842_s_ctrl()
1234 cp_write(sd, 0xc0, G); in adv7842_s_ctrl()
1235 cp_write(sd, 0xc2, B); in adv7842_s_ctrl()
1237 sdp_write(sd, 0xde, Y); in adv7842_s_ctrl()
1238 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); in adv7842_s_ctrl()
1243 set_rgb_quantization_range(sd); in adv7842_s_ctrl()
1249 static inline bool no_power(struct v4l2_subdev *sd) in no_power() argument
1251 return io_read(sd, 0x0c) & 0x24; in no_power()
1254 static inline bool no_cp_signal(struct v4l2_subdev *sd) in no_cp_signal() argument
1256 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); in no_cp_signal()
1259 static inline bool is_hdmi(struct v4l2_subdev *sd) in is_hdmi() argument
1261 return hdmi_read(sd, 0x05) & 0x80; in is_hdmi()
1264 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) in adv7842_g_input_status() argument
1266 struct adv7842_state *state = to_state(sd); in adv7842_g_input_status()
1270 if (io_read(sd, 0x0c) & 0x24) in adv7842_g_input_status()
1275 if (!(sdp_read(sd, 0x5A) & 0x01)) in adv7842_g_input_status()
1278 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", in adv7842_g_input_status()
1283 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || in adv7842_g_input_status()
1284 !(cp_read(sd, 0xb1) & 0x80)) in adv7842_g_input_status()
1288 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) in adv7842_g_input_status()
1291 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", in adv7842_g_input_status()
1303 static int stdi2dv_timings(struct v4l2_subdev *sd, in stdi2dv_timings() argument
1307 struct adv7842_state *state = to_state(sd); in stdi2dv_timings()
1316 adv7842_get_dv_timings_cap(sd), in stdi2dv_timings()
1344 v4l2_dbg(2, debug, sd, in stdi2dv_timings()
1351 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) in read_stdi() argument
1355 adv7842_g_input_status(sd, &status); in read_stdi()
1357 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); in read_stdi()
1361 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in read_stdi()
1362 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in read_stdi()
1363 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1365 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { in read_stdi()
1366 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in read_stdi()
1367 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in read_stdi()
1368 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in read_stdi()
1369 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in read_stdi()
1374 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; in read_stdi()
1377 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); in read_stdi()
1381 v4l2_dbg(2, debug, sd, in read_stdi()
1390 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, in adv7842_enum_dv_timings() argument
1397 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); in adv7842_enum_dv_timings()
1400 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, in adv7842_dv_timings_cap() argument
1406 *cap = *adv7842_get_dv_timings_cap(sd); in adv7842_dv_timings_cap()
1412 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, in adv7842_fill_optional_dv_timings_fields() argument
1415 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), in adv7842_fill_optional_dv_timings_fields()
1416 is_digital_input(sd) ? 250000 : 1000000, in adv7842_fill_optional_dv_timings_fields()
1420 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, in adv7842_query_dv_timings() argument
1423 struct adv7842_state *state = to_state(sd); in adv7842_query_dv_timings()
1427 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_query_dv_timings()
1436 if (read_stdi(sd, &stdi)) { in adv7842_query_dv_timings()
1438 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); in adv7842_query_dv_timings()
1444 if (is_digital_input(sd)) { in adv7842_query_dv_timings()
1449 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); in adv7842_query_dv_timings()
1450 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); in adv7842_query_dv_timings()
1451 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; in adv7842_query_dv_timings()
1452 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); in adv7842_query_dv_timings()
1453 if (is_hdmi(sd)) { in adv7842_query_dv_timings()
1455 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); in adv7842_query_dv_timings()
1458 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + in adv7842_query_dv_timings()
1459 hdmi_read(sd, 0x21); in adv7842_query_dv_timings()
1460 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + in adv7842_query_dv_timings()
1461 hdmi_read(sd, 0x23); in adv7842_query_dv_timings()
1462 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + in adv7842_query_dv_timings()
1463 hdmi_read(sd, 0x25); in adv7842_query_dv_timings()
1464 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + in adv7842_query_dv_timings()
1465 hdmi_read(sd, 0x2b)) / 2; in adv7842_query_dv_timings()
1466 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + in adv7842_query_dv_timings()
1467 hdmi_read(sd, 0x2f)) / 2; in adv7842_query_dv_timings()
1468 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + in adv7842_query_dv_timings()
1469 hdmi_read(sd, 0x33)) / 2; in adv7842_query_dv_timings()
1470 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv7842_query_dv_timings()
1471 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); in adv7842_query_dv_timings()
1473 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + in adv7842_query_dv_timings()
1474 hdmi_read(sd, 0x0c); in adv7842_query_dv_timings()
1475 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + in adv7842_query_dv_timings()
1476 hdmi_read(sd, 0x2d)) / 2; in adv7842_query_dv_timings()
1477 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + in adv7842_query_dv_timings()
1478 hdmi_read(sd, 0x31)) / 2; in adv7842_query_dv_timings()
1479 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + in adv7842_query_dv_timings()
1480 hdmi_read(sd, 0x35)) / 2; in adv7842_query_dv_timings()
1482 adv7842_fill_optional_dv_timings_fields(sd, timings); in adv7842_query_dv_timings()
1488 if (!stdi2dv_timings(sd, &stdi, timings)) in adv7842_query_dv_timings()
1491 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); in adv7842_query_dv_timings()
1492 if (!stdi2dv_timings(sd, &stdi, timings)) in adv7842_query_dv_timings()
1495 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); in adv7842_query_dv_timings()
1496 if (stdi2dv_timings(sd, &stdi, timings)) { in adv7842_query_dv_timings()
1507 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); in adv7842_query_dv_timings()
1510 cp_write_and_or(sd, 0x86, 0xf9, 0x00); in adv7842_query_dv_timings()
1512 cp_write_and_or(sd, 0x86, 0xf9, 0x04); in adv7842_query_dv_timings()
1514 cp_write_and_or(sd, 0x86, 0xf9, 0x02); in adv7842_query_dv_timings()
1518 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); in adv7842_query_dv_timings()
1526 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", in adv7842_query_dv_timings()
1531 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, in adv7842_s_dv_timings() argument
1534 struct adv7842_state *state = to_state(sd); in adv7842_s_dv_timings()
1538 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_s_dv_timings()
1544 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); in adv7842_s_dv_timings()
1550 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), in adv7842_s_dv_timings()
1554 adv7842_fill_optional_dv_timings_fields(sd, timings); in adv7842_s_dv_timings()
1558 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); in adv7842_s_dv_timings()
1561 err = configure_predefined_video_timings(sd, timings); in adv7842_s_dv_timings()
1565 configure_custom_video_timings(sd, bt); in adv7842_s_dv_timings()
1568 set_rgb_quantization_range(sd); in adv7842_s_dv_timings()
1572 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", in adv7842_s_dv_timings()
1577 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, in adv7842_g_dv_timings() argument
1580 struct adv7842_state *state = to_state(sd); in adv7842_g_dv_timings()
1588 static void enable_input(struct v4l2_subdev *sd) in enable_input() argument
1590 struct adv7842_state *state = to_state(sd); in enable_input()
1592 set_rgb_quantization_range(sd); in enable_input()
1597 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ in enable_input()
1600 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ in enable_input()
1601 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ in enable_input()
1602 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ in enable_input()
1605 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in enable_input()
1611 static void disable_input(struct v4l2_subdev *sd) in disable_input() argument
1613 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ in disable_input()
1615 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ in disable_input()
1616 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ in disable_input()
1619 static void sdp_csc_coeff(struct v4l2_subdev *sd, in sdp_csc_coeff() argument
1623 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); in sdp_csc_coeff()
1629 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); in sdp_csc_coeff()
1632 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); in sdp_csc_coeff()
1633 sdp_io_write(sd, 0xe1, c->A1); in sdp_csc_coeff()
1634 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); in sdp_csc_coeff()
1635 sdp_io_write(sd, 0xe3, c->A2); in sdp_csc_coeff()
1636 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); in sdp_csc_coeff()
1637 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
1640 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); in sdp_csc_coeff()
1641 sdp_io_write(sd, 0xe7, c->A4); in sdp_csc_coeff()
1644 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); in sdp_csc_coeff()
1645 sdp_io_write(sd, 0xe9, c->B1); in sdp_csc_coeff()
1646 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); in sdp_csc_coeff()
1647 sdp_io_write(sd, 0xeb, c->B2); in sdp_csc_coeff()
1648 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); in sdp_csc_coeff()
1649 sdp_io_write(sd, 0xed, c->B3); in sdp_csc_coeff()
1652 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); in sdp_csc_coeff()
1653 sdp_io_write(sd, 0xef, c->B4); in sdp_csc_coeff()
1656 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); in sdp_csc_coeff()
1657 sdp_io_write(sd, 0xf1, c->C1); in sdp_csc_coeff()
1658 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); in sdp_csc_coeff()
1659 sdp_io_write(sd, 0xf3, c->C2); in sdp_csc_coeff()
1660 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); in sdp_csc_coeff()
1661 sdp_io_write(sd, 0xf5, c->C3); in sdp_csc_coeff()
1664 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); in sdp_csc_coeff()
1665 sdp_io_write(sd, 0xf7, c->C4); in sdp_csc_coeff()
1668 static void select_input(struct v4l2_subdev *sd, in select_input() argument
1671 struct adv7842_state *state = to_state(sd); in select_input()
1675 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ in select_input()
1676 io_write(sd, 0x01, 0); /* prim mode */ in select_input()
1678 cp_write_and_or(sd, 0x81, 0xef, 0x10); in select_input()
1680 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1681 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1683 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ in select_input()
1687 afe_write_and_or(sd, 0x02, 0x7f, 0x80); in select_input()
1689 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ in select_input()
1690 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ in select_input()
1692 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ in select_input()
1693 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ in select_input()
1695 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ in select_input()
1696 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ in select_input()
1698 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ in select_input()
1699 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ in select_input()
1702 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ in select_input()
1703 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ in select_input()
1705 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ in select_input()
1706 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ in select_input()
1707 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ in select_input()
1708 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ in select_input()
1709 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ in select_input()
1710 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ in select_input()
1711 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ in select_input()
1714 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); in select_input()
1721 afe_write_and_or(sd, 0x02, 0x7f, 0x00); in select_input()
1723 io_write(sd, 0x00, vid_std_select); /* video std */ in select_input()
1724 io_write(sd, 0x01, 0x02); /* prim mode */ in select_input()
1725 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs in select_input()
1728 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1729 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1732 io_write_and_or(sd, 0x02, 0x0f, 0x60); in select_input()
1735 io_write_and_or(sd, 0x02, 0x0f, 0x10); in select_input()
1741 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ in select_input()
1742 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ in select_input()
1745 cp_write(sd, 0x73, 0x10); in select_input()
1746 cp_write(sd, 0x74, 0x04); in select_input()
1747 cp_write(sd, 0x75, 0x01); in select_input()
1748 cp_write(sd, 0x76, 0x00); in select_input()
1750 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ in select_input()
1751 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ in select_input()
1752 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ in select_input()
1757 afe_write_and_or(sd, 0x02, 0x7f, 0x00); in select_input()
1760 hdmi_write(sd, 0x00, 0x02); /* select port A */ in select_input()
1762 hdmi_write(sd, 0x00, 0x03); /* select port B */ in select_input()
1763 io_write(sd, 0x00, vid_std_select); /* video std */ in select_input()
1764 io_write(sd, 0x01, 5); /* prim mode */ in select_input()
1765 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs in select_input()
1771 hdmi_write(sd, 0xc0, 0x00); in select_input()
1772 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ in select_input()
1773 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ in select_input()
1774 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ in select_input()
1775 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ in select_input()
1776 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ in select_input()
1777 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ in select_input()
1778 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ in select_input()
1779 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ in select_input()
1780 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, in select_input()
1782 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ in select_input()
1783 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ in select_input()
1784 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ in select_input()
1785 hdmi_write(sd, 0x89, 0x04); /* equaliser */ in select_input()
1786 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ in select_input()
1787 hdmi_write(sd, 0x93, 0x04); /* equaliser */ in select_input()
1788 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ in select_input()
1789 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ in select_input()
1790 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ in select_input()
1791 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ in select_input()
1793 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1794 afe_write(sd, 0xc8, 0x40); /* phase control */ in select_input()
1797 cp_write(sd, 0x73, 0x10); in select_input()
1798 cp_write(sd, 0x74, 0x04); in select_input()
1799 cp_write(sd, 0x75, 0x01); in select_input()
1800 cp_write(sd, 0x76, 0x00); in select_input()
1805 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ in select_input()
1806 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ in select_input()
1807 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1810 cp_write(sd, 0xc3, 0x33); /* Component mode */ in select_input()
1813 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in select_input()
1817 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in select_input()
1823 static int adv7842_s_routing(struct v4l2_subdev *sd, in adv7842_s_routing() argument
1826 struct adv7842_state *state = to_state(sd); in adv7842_s_routing()
1828 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); in adv7842_s_routing()
1861 disable_input(sd); in adv7842_s_routing()
1862 select_input(sd, state->vid_std_select); in adv7842_s_routing()
1863 enable_input(sd); in adv7842_s_routing()
1865 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); in adv7842_s_routing()
1870 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, in adv7842_enum_mbus_fmt() argument
1880 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd, in adv7842_g_mbus_fmt() argument
1883 struct adv7842_state *state = to_state(sd); in adv7842_g_mbus_fmt()
1892 if (!(sdp_read(sd, 0x5A) & 0x01)) in adv7842_g_mbus_fmt()
1912 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) in adv7842_irq_enable() argument
1916 io_write(sd, 0x46, 0x9c); in adv7842_irq_enable()
1918 io_write(sd, 0x5a, 0x10); in adv7842_irq_enable()
1920 io_write(sd, 0x73, 0x03); in adv7842_irq_enable()
1922 io_write(sd, 0x78, 0x03); in adv7842_irq_enable()
1924 io_write(sd, 0xa0, 0x09); in adv7842_irq_enable()
1926 io_write(sd, 0x69, 0x08); in adv7842_irq_enable()
1928 io_write(sd, 0x46, 0x0); in adv7842_irq_enable()
1929 io_write(sd, 0x5a, 0x0); in adv7842_irq_enable()
1930 io_write(sd, 0x73, 0x0); in adv7842_irq_enable()
1931 io_write(sd, 0x78, 0x0); in adv7842_irq_enable()
1932 io_write(sd, 0xa0, 0x0); in adv7842_irq_enable()
1933 io_write(sd, 0x69, 0x0); in adv7842_irq_enable()
1937 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) in adv7842_isr() argument
1939 struct adv7842_state *state = to_state(sd); in adv7842_isr()
1943 adv7842_irq_enable(sd, false); in adv7842_isr()
1946 irq_status[0] = io_read(sd, 0x43); in adv7842_isr()
1947 irq_status[1] = io_read(sd, 0x57); in adv7842_isr()
1948 irq_status[2] = io_read(sd, 0x70); in adv7842_isr()
1949 irq_status[3] = io_read(sd, 0x75); in adv7842_isr()
1950 irq_status[4] = io_read(sd, 0x9d); in adv7842_isr()
1951 irq_status[5] = io_read(sd, 0x66); in adv7842_isr()
1955 io_write(sd, 0x44, irq_status[0]); in adv7842_isr()
1957 io_write(sd, 0x58, irq_status[1]); in adv7842_isr()
1959 io_write(sd, 0x71, irq_status[2]); in adv7842_isr()
1961 io_write(sd, 0x76, irq_status[3]); in adv7842_isr()
1963 io_write(sd, 0x9e, irq_status[4]); in adv7842_isr()
1965 io_write(sd, 0x67, irq_status[5]); in adv7842_isr()
1967 adv7842_irq_enable(sd, true); in adv7842_isr()
1969 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, in adv7842_isr()
1983 if (is_digital_input(sd)) in adv7842_isr()
1990 v4l2_dbg(1, debug, sd, in adv7842_isr()
1994 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); in adv7842_isr()
2001 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, in adv7842_isr()
2002 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); in adv7842_isr()
2003 set_rgb_quantization_range(sd); in adv7842_isr()
2010 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); in adv7842_isr()
2011 adv7842_s_detect_tx_5v_ctrl(sd); in adv7842_isr()
2018 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) in adv7842_get_edid() argument
2020 struct adv7842_state *state = to_state(sd); in adv7842_get_edid()
2058 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) in adv7842_set_edid() argument
2060 struct adv7842_state *state = to_state(sd); in adv7842_set_edid()
2083 err = edid_write_vga_segment(sd); in adv7842_set_edid()
2093 err = edid_write_hdmi_segment(sd, e->pad); in adv7842_set_edid()
2099 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); in adv7842_set_edid()
2110 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri) in log_infoframe() argument
2116 struct i2c_client *client = v4l2_get_subdevdata(sd); in log_infoframe()
2119 if (!(io_read(sd, 0x60) & cri->present_mask)) { in log_infoframe()
2120 v4l2_info(sd, "%s infoframe not received\n", cri->desc); in log_infoframe()
2125 buffer[i] = infoframe_read(sd, cri->head_addr + i); in log_infoframe()
2130 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); in log_infoframe()
2135 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); in log_infoframe()
2138 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); in log_infoframe()
2145 static void adv7842_log_infoframes(struct v4l2_subdev *sd) in adv7842_log_infoframes() argument
2155 if (!(hdmi_read(sd, 0x05) & 0x80)) { in adv7842_log_infoframes()
2156 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); in adv7842_log_infoframes()
2161 log_infoframe(sd, &cri[i]); in adv7842_log_infoframes()
2183 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) in adv7842_sdp_log_status() argument
2186 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; in adv7842_sdp_log_status()
2188 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); in adv7842_sdp_log_status()
2189 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", in adv7842_sdp_log_status()
2190 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); in adv7842_sdp_log_status()
2192 v4l2_info(sd, "SDP: free run: %s\n", in adv7842_sdp_log_status()
2193 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); in adv7842_sdp_log_status()
2194 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? in adv7842_sdp_log_status()
2211 v4l2_info(sd, "SDP: standard %s\n", in adv7842_sdp_log_status()
2212 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); in adv7842_sdp_log_status()
2213 v4l2_info(sd, "SDP: %s\n", in adv7842_sdp_log_status()
2214 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); in adv7842_sdp_log_status()
2215 v4l2_info(sd, "SDP: %s\n", in adv7842_sdp_log_status()
2216 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); in adv7842_sdp_log_status()
2217 v4l2_info(sd, "SDP: deinterlacer %s\n", in adv7842_sdp_log_status()
2218 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); in adv7842_sdp_log_status()
2219 v4l2_info(sd, "SDP: csc %s mode\n", in adv7842_sdp_log_status()
2220 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); in adv7842_sdp_log_status()
2225 static int adv7842_cp_log_status(struct v4l2_subdev *sd) in adv7842_cp_log_status() argument
2228 struct adv7842_state *state = to_state(sd); in adv7842_cp_log_status()
2230 uint8_t reg_io_0x02 = io_read(sd, 0x02); in adv7842_cp_log_status()
2231 uint8_t reg_io_0x21 = io_read(sd, 0x21); in adv7842_cp_log_status()
2232 uint8_t reg_rep_0x77 = rep_read(sd, 0x77); in adv7842_cp_log_status()
2233 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d); in adv7842_cp_log_status()
2234 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; in adv7842_cp_log_status()
2235 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; in adv7842_cp_log_status()
2236 bool audio_mute = io_read(sd, 0x65) & 0x40; in adv7842_cp_log_status()
2264 v4l2_info(sd, "-----Chip status-----\n"); in adv7842_cp_log_status()
2265 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); in adv7842_cp_log_status()
2266 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", in adv7842_cp_log_status()
2268 v4l2_info(sd, "EDID A %s, B %s\n", in adv7842_cp_log_status()
2273 v4l2_info(sd, "HPD A %s, B %s\n", in adv7842_cp_log_status()
2276 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? in adv7842_cp_log_status()
2279 v4l2_info(sd, "-----Signal status-----\n"); in adv7842_cp_log_status()
2281 v4l2_info(sd, "Cable detected (+5V power): %s\n", in adv7842_cp_log_status()
2282 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); in adv7842_cp_log_status()
2283 v4l2_info(sd, "TMDS signal detected: %s\n", in adv7842_cp_log_status()
2284 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); in adv7842_cp_log_status()
2285 v4l2_info(sd, "TMDS signal locked: %s\n", in adv7842_cp_log_status()
2286 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); in adv7842_cp_log_status()
2288 v4l2_info(sd, "Cable detected (+5V power):%s\n", in adv7842_cp_log_status()
2289 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); in adv7842_cp_log_status()
2290 v4l2_info(sd, "TMDS signal detected: %s\n", in adv7842_cp_log_status()
2291 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); in adv7842_cp_log_status()
2292 v4l2_info(sd, "TMDS signal locked: %s\n", in adv7842_cp_log_status()
2293 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); in adv7842_cp_log_status()
2295 v4l2_info(sd, "CP free run: %s\n", in adv7842_cp_log_status()
2296 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); in adv7842_cp_log_status()
2297 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv7842_cp_log_status()
2298 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, in adv7842_cp_log_status()
2299 (io_read(sd, 0x01) & 0x70) >> 4); in adv7842_cp_log_status()
2301 v4l2_info(sd, "-----Video Timings-----\n"); in adv7842_cp_log_status()
2302 if (no_cp_signal(sd)) { in adv7842_cp_log_status()
2303 v4l2_info(sd, "STDI: not locked\n"); in adv7842_cp_log_status()
2305 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in adv7842_cp_log_status()
2306 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in adv7842_cp_log_status()
2307 uint32_t lcvs = cp_read(sd, 0xb3) >> 3; in adv7842_cp_log_status()
2308 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); in adv7842_cp_log_status()
2309 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in adv7842_cp_log_status()
2310 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2311 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in adv7842_cp_log_status()
2312 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2313 v4l2_info(sd, in adv7842_cp_log_status()
2316 (cp_read(sd, 0xb1) & 0x40) ? in adv7842_cp_log_status()
2320 if (adv7842_query_dv_timings(sd, &timings)) in adv7842_cp_log_status()
2321 v4l2_info(sd, "No video detected\n"); in adv7842_cp_log_status()
2323 v4l2_print_dv_timings(sd->name, "Detected format: ", in adv7842_cp_log_status()
2325 v4l2_print_dv_timings(sd->name, "Configured format: ", in adv7842_cp_log_status()
2328 if (no_cp_signal(sd)) in adv7842_cp_log_status()
2331 v4l2_info(sd, "-----Color space-----\n"); in adv7842_cp_log_status()
2332 v4l2_info(sd, "RGB quantization range ctrl: %s\n", in adv7842_cp_log_status()
2334 v4l2_info(sd, "Input color space: %s\n", in adv7842_cp_log_status()
2336 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", in adv7842_cp_log_status()
2341 v4l2_info(sd, "Color space conversion: %s\n", in adv7842_cp_log_status()
2342 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); in adv7842_cp_log_status()
2344 if (!is_digital_input(sd)) in adv7842_cp_log_status()
2347 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); in adv7842_cp_log_status()
2348 v4l2_info(sd, "HDCP encrypted content: %s\n", in adv7842_cp_log_status()
2349 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); in adv7842_cp_log_status()
2350 v4l2_info(sd, "HDCP keys read: %s%s\n", in adv7842_cp_log_status()
2351 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", in adv7842_cp_log_status()
2352 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); in adv7842_cp_log_status()
2353 if (!is_hdmi(sd)) in adv7842_cp_log_status()
2356 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", in adv7842_cp_log_status()
2361 v4l2_info(sd, "Audio format: %s\n", in adv7842_cp_log_status()
2362 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); in adv7842_cp_log_status()
2364 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + in adv7842_cp_log_status()
2365 (hdmi_read(sd, 0x5c) << 8) + in adv7842_cp_log_status()
2366 (hdmi_read(sd, 0x5d) & 0xf0)); in adv7842_cp_log_status()
2367 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + in adv7842_cp_log_status()
2368 (hdmi_read(sd, 0x5e) << 8) + in adv7842_cp_log_status()
2369 hdmi_read(sd, 0x5f)); in adv7842_cp_log_status()
2370 v4l2_info(sd, "AV Mute: %s\n", in adv7842_cp_log_status()
2371 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); in adv7842_cp_log_status()
2372 v4l2_info(sd, "Deep color mode: %s\n", in adv7842_cp_log_status()
2373 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); in adv7842_cp_log_status()
2375 adv7842_log_infoframes(sd); in adv7842_cp_log_status()
2380 static int adv7842_log_status(struct v4l2_subdev *sd) in adv7842_log_status() argument
2382 struct adv7842_state *state = to_state(sd); in adv7842_log_status()
2385 return adv7842_sdp_log_status(sd); in adv7842_log_status()
2386 return adv7842_cp_log_status(sd); in adv7842_log_status()
2389 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) in adv7842_querystd() argument
2391 struct adv7842_state *state = to_state(sd); in adv7842_querystd()
2393 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_querystd()
2398 if (!(sdp_read(sd, 0x5A) & 0x01)) { in adv7842_querystd()
2400 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); in adv7842_querystd()
2404 switch (sdp_read(sd, 0x52) & 0x0f) { in adv7842_querystd()
2444 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) in adv7842_s_sdp_io() argument
2447 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2448 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); in adv7842_s_sdp_io()
2449 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); in adv7842_s_sdp_io()
2450 sdp_io_write(sd, 0x97, s->hs_width & 0xff); in adv7842_s_sdp_io()
2451 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2452 sdp_io_write(sd, 0x99, s->de_beg & 0xff); in adv7842_s_sdp_io()
2453 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); in adv7842_s_sdp_io()
2454 sdp_io_write(sd, 0x9b, s->de_end & 0xff); in adv7842_s_sdp_io()
2455 sdp_io_write(sd, 0xa8, s->vs_beg_o); in adv7842_s_sdp_io()
2456 sdp_io_write(sd, 0xa9, s->vs_beg_e); in adv7842_s_sdp_io()
2457 sdp_io_write(sd, 0xaa, s->vs_end_o); in adv7842_s_sdp_io()
2458 sdp_io_write(sd, 0xab, s->vs_end_e); in adv7842_s_sdp_io()
2459 sdp_io_write(sd, 0xac, s->de_v_beg_o); in adv7842_s_sdp_io()
2460 sdp_io_write(sd, 0xad, s->de_v_beg_e); in adv7842_s_sdp_io()
2461 sdp_io_write(sd, 0xae, s->de_v_end_o); in adv7842_s_sdp_io()
2462 sdp_io_write(sd, 0xaf, s->de_v_end_e); in adv7842_s_sdp_io()
2465 sdp_io_write(sd, 0x94, 0x00); in adv7842_s_sdp_io()
2466 sdp_io_write(sd, 0x95, 0x00); in adv7842_s_sdp_io()
2467 sdp_io_write(sd, 0x96, 0x00); in adv7842_s_sdp_io()
2468 sdp_io_write(sd, 0x97, 0x20); in adv7842_s_sdp_io()
2469 sdp_io_write(sd, 0x98, 0x00); in adv7842_s_sdp_io()
2470 sdp_io_write(sd, 0x99, 0x00); in adv7842_s_sdp_io()
2471 sdp_io_write(sd, 0x9a, 0x00); in adv7842_s_sdp_io()
2472 sdp_io_write(sd, 0x9b, 0x00); in adv7842_s_sdp_io()
2473 sdp_io_write(sd, 0xa8, 0x04); in adv7842_s_sdp_io()
2474 sdp_io_write(sd, 0xa9, 0x04); in adv7842_s_sdp_io()
2475 sdp_io_write(sd, 0xaa, 0x04); in adv7842_s_sdp_io()
2476 sdp_io_write(sd, 0xab, 0x04); in adv7842_s_sdp_io()
2477 sdp_io_write(sd, 0xac, 0x04); in adv7842_s_sdp_io()
2478 sdp_io_write(sd, 0xad, 0x04); in adv7842_s_sdp_io()
2479 sdp_io_write(sd, 0xae, 0x04); in adv7842_s_sdp_io()
2480 sdp_io_write(sd, 0xaf, 0x04); in adv7842_s_sdp_io()
2484 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) in adv7842_s_std() argument
2486 struct adv7842_state *state = to_state(sd); in adv7842_s_std()
2489 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_s_std()
2495 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); in adv7842_s_std()
2497 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); in adv7842_s_std()
2499 adv7842_s_sdp_io(sd, NULL); in adv7842_s_std()
2508 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) in adv7842_g_std() argument
2510 struct adv7842_state *state = to_state(sd); in adv7842_g_std()
2512 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_g_std()
2523 static int adv7842_core_init(struct v4l2_subdev *sd) in adv7842_core_init() argument
2525 struct adv7842_state *state = to_state(sd); in adv7842_core_init()
2527 hdmi_write(sd, 0x48, in adv7842_core_init()
2531 disable_input(sd); in adv7842_core_init()
2537 rep_write_and_or(sd, 0x77, 0xd3, 0x20); in adv7842_core_init()
2540 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ in adv7842_core_init()
2541 io_write(sd, 0x15, 0x80); /* Power up pads */ in adv7842_core_init()
2544 io_write(sd, 0x02, in adv7842_core_init()
2550 io_write(sd, 0x03, pdata->op_format_sel); in adv7842_core_init()
2551 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); in adv7842_core_init()
2552 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | in adv7842_core_init()
2558 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ in adv7842_core_init()
2561 io_write_and_or(sd, 0x14, 0xc0, in adv7842_core_init()
2567 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | in adv7842_core_init()
2571 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | in adv7842_core_init()
2577 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ in adv7842_core_init()
2578 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ in adv7842_core_init()
2579 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ in adv7842_core_init()
2580 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ in adv7842_core_init()
2582 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv7842_core_init()
2583 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); in adv7842_core_init()
2585 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); in adv7842_core_init()
2589 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ in adv7842_core_init()
2592 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ in adv7842_core_init()
2593 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ in adv7842_core_init()
2594 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
2595 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
2596 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
2598 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ in adv7842_core_init()
2599 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ in adv7842_core_init()
2600 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, in adv7842_core_init()
2602 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ in adv7842_core_init()
2603 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
2604 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
2605 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
2612 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ in adv7842_core_init()
2615 select_input(sd, pdata->vid_std_select); in adv7842_core_init()
2617 enable_input(sd); in adv7842_core_init()
2621 hdmi_write(sd, 0x69, 0x5c); in adv7842_core_init()
2624 hdmi_write(sd, 0x69, 0xa3); in adv7842_core_init()
2626 io_write_and_or(sd, 0x20, 0xcf, 0x00); in adv7842_core_init()
2630 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); in adv7842_core_init()
2631 io_write(sd, 0x33, 0x40); in adv7842_core_init()
2634 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ in adv7842_core_init()
2636 adv7842_irq_enable(sd, true); in adv7842_core_init()
2638 return v4l2_ctrl_handler_setup(sd->ctrl_handler); in adv7842_core_init()
2643 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) in adv7842_ddr_ram_test() argument
2656 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ in adv7842_ddr_ram_test()
2657 io_write(sd, 0x01, 0x00); /* Program SDP mode */ in adv7842_ddr_ram_test()
2658 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ in adv7842_ddr_ram_test()
2659 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2660 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2661 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2662 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2663 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2664 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ in adv7842_ddr_ram_test()
2665 io_write(sd, 0x15, 0xBA); /* Enable outputs */ in adv7842_ddr_ram_test()
2666 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ in adv7842_ddr_ram_test()
2667 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ in adv7842_ddr_ram_test()
2671 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ in adv7842_ddr_ram_test()
2672 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2673 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2674 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2675 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2676 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2677 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2678 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2679 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2680 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2681 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2685 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ in adv7842_ddr_ram_test()
2686 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ in adv7842_ddr_ram_test()
2691 u8 result = sdp_io_read(sd, 0xdb); in adv7842_ddr_ram_test()
2702 v4l2_dbg(1, debug, sd, in adv7842_ddr_ram_test()
2711 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, in adv7842_rewrite_i2c_addresses() argument
2714 io_write(sd, 0xf1, pdata->i2c_sdp << 1); in adv7842_rewrite_i2c_addresses()
2715 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); in adv7842_rewrite_i2c_addresses()
2716 io_write(sd, 0xf3, pdata->i2c_avlink << 1); in adv7842_rewrite_i2c_addresses()
2717 io_write(sd, 0xf4, pdata->i2c_cec << 1); in adv7842_rewrite_i2c_addresses()
2718 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); in adv7842_rewrite_i2c_addresses()
2720 io_write(sd, 0xf8, pdata->i2c_afe << 1); in adv7842_rewrite_i2c_addresses()
2721 io_write(sd, 0xf9, pdata->i2c_repeater << 1); in adv7842_rewrite_i2c_addresses()
2722 io_write(sd, 0xfa, pdata->i2c_edid << 1); in adv7842_rewrite_i2c_addresses()
2723 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); in adv7842_rewrite_i2c_addresses()
2725 io_write(sd, 0xfd, pdata->i2c_cp << 1); in adv7842_rewrite_i2c_addresses()
2726 io_write(sd, 0xfe, pdata->i2c_vdp << 1); in adv7842_rewrite_i2c_addresses()
2729 static int adv7842_command_ram_test(struct v4l2_subdev *sd) in adv7842_command_ram_test() argument
2731 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv7842_command_ram_test()
2732 struct adv7842_state *state = to_state(sd); in adv7842_command_ram_test()
2741 v4l2_info(sd, "no sdram or no ddr sdram\n"); in adv7842_command_ram_test()
2745 main_reset(sd); in adv7842_command_ram_test()
2747 adv7842_rewrite_i2c_addresses(sd, pdata); in adv7842_command_ram_test()
2750 ret = adv7842_ddr_ram_test(sd); in adv7842_command_ram_test()
2752 main_reset(sd); in adv7842_command_ram_test()
2754 adv7842_rewrite_i2c_addresses(sd, pdata); in adv7842_command_ram_test()
2757 adv7842_core_init(sd); in adv7842_command_ram_test()
2759 disable_input(sd); in adv7842_command_ram_test()
2761 select_input(sd, state->vid_std_select); in adv7842_command_ram_test()
2763 enable_input(sd); in adv7842_command_ram_test()
2765 edid_write_vga_segment(sd); in adv7842_command_ram_test()
2766 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); in adv7842_command_ram_test()
2767 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); in adv7842_command_ram_test()
2773 adv7842_s_dv_timings(sd, &timings); in adv7842_command_ram_test()
2778 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) in adv7842_ioctl() argument
2782 return adv7842_command_ram_test(sd); in adv7842_ioctl()
2864 static void adv7842_unregister_clients(struct v4l2_subdev *sd) in adv7842_unregister_clients() argument
2866 struct adv7842_state *state = to_state(sd); in adv7842_unregister_clients()
2903 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, in adv7842_dummy_client() argument
2906 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv7842_dummy_client()
2909 io_write(sd, io_reg, addr << 1); in adv7842_dummy_client()
2912 v4l2_err(sd, "no %s i2c addr configured\n", desc); in adv7842_dummy_client()
2916 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); in adv7842_dummy_client()
2918 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr); in adv7842_dummy_client()
2923 static int adv7842_register_clients(struct v4l2_subdev *sd) in adv7842_register_clients() argument
2925 struct adv7842_state *state = to_state(sd); in adv7842_register_clients()
2928 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); in adv7842_register_clients()
2929 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); in adv7842_register_clients()
2930 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); in adv7842_register_clients()
2931 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); in adv7842_register_clients()
2932 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); in adv7842_register_clients()
2933 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); in adv7842_register_clients()
2934 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); in adv7842_register_clients()
2935 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); in adv7842_register_clients()
2936 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); in adv7842_register_clients()
2937 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); in adv7842_register_clients()
2938 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); in adv7842_register_clients()
2964 struct v4l2_subdev *sd; in adv7842_probe() local
2990 sd = &state->sd; in adv7842_probe()
2991 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); in adv7842_probe()
2992 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; in adv7842_probe()
3002 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); in adv7842_probe()
3007 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", in adv7842_probe()
3013 main_reset(sd); in adv7842_probe()
3042 sd->ctrl_handler = hdl; in adv7842_probe()
3053 if (adv7842_s_detect_tx_5v_ctrl(sd)) { in adv7842_probe()
3058 if (adv7842_register_clients(sd) < 0) { in adv7842_probe()
3060 v4l2_err(sd, "failed to create all i2c clients\n"); in adv7842_probe()
3067 v4l2_err(sd, "Could not create work queue\n"); in adv7842_probe()
3076 err = media_entity_init(&sd->entity, 1, &state->pad, 0); in adv7842_probe()
3080 err = adv7842_core_init(sd); in adv7842_probe()
3084 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv7842_probe()
3089 media_entity_cleanup(&sd->entity); in adv7842_probe()
3094 adv7842_unregister_clients(sd); in adv7842_probe()
3104 struct v4l2_subdev *sd = i2c_get_clientdata(client); in adv7842_remove() local
3105 struct adv7842_state *state = to_state(sd); in adv7842_remove()
3107 adv7842_irq_enable(sd, false); in adv7842_remove()
3111 v4l2_device_unregister_subdev(sd); in adv7842_remove()
3112 media_entity_cleanup(&sd->entity); in adv7842_remove()
3113 adv7842_unregister_clients(sd); in adv7842_remove()
3114 v4l2_ctrl_handler_free(sd->ctrl_handler); in adv7842_remove()