430 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in afe_write()  function
439 	return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);  in afe_write_and_or()
844 		afe_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
1205 		afe_write(sd, 0xc8, ctrl->val);  in adv7842_s_ctrl()
1680 		afe_write(sd, 0x00, 0x00); /* power up ADC */  in select_input()
1681 		afe_write(sd, 0xc8, 0x00); /* phase control */  in select_input()
1689 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/  in select_input()
1690 			afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/  in select_input()
1692 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/  in select_input()
1693 			afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/  in select_input()
1695 		afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */  in select_input()
1696 		afe_write(sd, 0x12, 0x63); /* ADI recommend write */  in select_input()
1728 		afe_write(sd, 0x00, 0x00); /* power up ADC */  in select_input()
1729 		afe_write(sd, 0xc8, 0x00); /* phase control */  in select_input()
1741 		afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */  in select_input()
1742 		afe_write(sd, 0x12, 0x63); /* ADC Range improvement */  in select_input()
1793 		afe_write(sd, 0x00, 0xff); /* power down ADC */  in select_input()
1794 		afe_write(sd, 0xc8, 0x40); /* phase control */  in select_input()
1805 		afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */  in select_input()
1806 		afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */  in select_input()
2580 	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */  in adv7842_core_init()
2582 	afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */  in adv7842_core_init()
2658 	afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */  in adv7842_ddr_ram_test()
2659 	afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */  in adv7842_ddr_ram_test()
2660 	afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */  in adv7842_ddr_ram_test()
2661 	afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */  in adv7842_ddr_ram_test()
2662 	afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */  in adv7842_ddr_ram_test()
2663 	afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()