79 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)  in s5h1420_readreg()  function
136 				 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);  in s5h1420_set_voltage()
140 		s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);  in s5h1420_set_voltage()
144 		s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);  in s5h1420_set_voltage()
160 				 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);  in s5h1420_set_tone()
165 				 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);  in s5h1420_set_tone()
187 	val = s5h1420_readreg(state, 0x3b);  in s5h1420_send_master_cmd()
197 	s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |  in s5h1420_send_master_cmd()
203 		if (!(s5h1420_readreg(state, 0x3b) & 0x08))  in s5h1420_send_master_cmd()
229 	val = s5h1420_readreg(state, 0x3b);  in s5h1420_recv_slave_reply()
236 		if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */  in s5h1420_recv_slave_reply()
248 	if (s5h1420_readreg(state, 0x49)) {  in s5h1420_recv_slave_reply()
254 	length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;  in s5h1420_recv_slave_reply()
263 		reply->msg[i] = s5h1420_readreg(state, 0x3d + i);  in s5h1420_recv_slave_reply()
281 	val = s5h1420_readreg(state, 0x3b);  in s5h1420_send_burst()
282 	s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);  in s5h1420_send_burst()
286 		s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);  in s5h1420_send_burst()
291 	s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);  in s5h1420_send_burst()
296 		if (!(s5h1420_readreg(state, 0x3b) & 0x08))  in s5h1420_send_burst()
315 	val = s5h1420_readreg(state, 0x14);  in s5h1420_get_status_bits()
320 	val = s5h1420_readreg(state, 0x36);  in s5h1420_get_status_bits()
347 		val = s5h1420_readreg(state, Vit10);  in s5h1420_read_status()
365 		switch (s5h1420_readreg(state, Vit10) & 0x07) {  in s5h1420_read_status()
405 		val = s5h1420_readreg(state, Mpeg02);  in s5h1420_read_status()
409 		val = s5h1420_readreg(state, QPSK01) & 0x7f;  in s5h1420_read_status()
438 	*ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);  in s5h1420_read_ber()
447 	u8 val = s5h1420_readreg(state, 0x15);  in s5h1420_read_signal_strength()
461 	*ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);  in s5h1420_read_ucblocks()
489 	v = s5h1420_readreg(state, Loop01);  in s5h1420_setsymbolrate()
516 	v = s5h1420_readreg(state, Loop01);  in s5h1420_setfreqoffset()
529 	s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);  in s5h1420_getfreqoffset()
530 	val  = s5h1420_readreg(state, 0x0e) << 16;  in s5h1420_getfreqoffset()
531 	val |= s5h1420_readreg(state, 0x0f) << 8;  in s5h1420_getfreqoffset()
532 	val |= s5h1420_readreg(state, 0x10);  in s5h1420_getfreqoffset()
533 	s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);  in s5h1420_getfreqoffset()
600 	switch(s5h1420_readreg(state, 0x32) & 0x07) {  in s5h1420_getfec()
625 	if (s5h1420_readreg(state, 0x32) & 0x08)  in s5h1420_getinversion()
737 	s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);  in s5h1420_set_frontend()
894 	i = s5h1420_readreg(state, ID01);  in s5h1420_attach()
901 		state->shadow[i] = s5h1420_readreg(state, i);  in s5h1420_attach()