Lines Matching refs:u16
87 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
88 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
89 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
90 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
91 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
93 u16 R1;
94 u16 R2;
95 u16 R3;
133 u16 hi_cfg_timing_div;
134 u16 hi_cfg_bridge_delay;
135 u16 hi_cfg_wakeup_key;
136 u16 hi_cfg_ctrl;
138 u16 intermediate_freq;
139 u16 osc_clock_freq;
144 u16 sys_clock_freq;
146 u16 expected_sys_clock_freq;
148 u16 insert_rs_byte;
149 u16 enable_parallel;
160 u16 current_fe_if_incr;
162 u16 m_FeAgRegAgPwd;
163 u16 m_FeAgRegAgAgcSio;
165 u16 m_EcOcRegOcModeLop;
166 u16 m_EcOcRegSncSncLvl;
241 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) in Read16()
271 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) in Write16()
317 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) in WriteBlock()
320 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; in WriteBlock()
339 u16 Length; in WriteTable()
348 pTable += sizeof(u16); in WriteTable()
414 u16 ocSyncLvl = 0; in StopOC()
415 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
416 u16 dtoIncLop = 0; in StopOC()
417 u16 dtoIncHip = 0; in StopOC()
533 u16 ScRaRamLock = 0; in DRX_GetLockStatus()
534 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M | in DRX_GetLockStatus()
537 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M | in DRX_GetLockStatus()
539 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M; in DRX_GetLockStatus()
578 u16 FeAgRegPm1AgcWri; in SetCfgIfAgc()
579 u16 FeAgRegAgModeLop; in SetCfgIfAgc()
590 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & in SetCfgIfAgc()
604 u16 FeAgRegAgModeLop; in SetCfgIfAgc()
605 u16 FeAgRegEgcSetLvl; in SetCfgIfAgc()
606 u16 slope, offset; in SetCfgIfAgc()
622 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & in SetCfgIfAgc()
630 slope = (u16) ((cfg->maxOutputLevel - in SetCfgIfAgc()
632 offset = (u16) ((cfg->maxOutputLevel + in SetCfgIfAgc()
644 const u16 maxRur = 8; in SetCfgIfAgc()
645 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 }; in SetCfgIfAgc()
646 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16, in SetCfgIfAgc()
653 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / in SetCfgIfAgc()
655 u16 fineSpeed = (u16) (cfg->speed - in SetCfgIfAgc()
659 u16 invRurCount = (u16) (cfg->speed / in SetCfgIfAgc()
661 u16 rurCount; in SetCfgIfAgc()
677 u16 fastIncrDec = in SetCfgIfAgc()
681 u16 slowIncrDec = in SetCfgIfAgc()
721 u16 AgModeLop = 0; in SetCfgRfAgc()
722 u16 level = (cfg->outputLevel); in SetCfgRfAgc()
754 u16 FeAgRegAgAgcSio = 0; in SetCfgRfAgc()
769 u16 AgModeLop = 0; in SetCfgRfAgc()
772 u16 level; in SetCfgRfAgc()
806 u16 FeAgRegAgAgcSio = 0; in SetCfgRfAgc()
821 u16 AgModeLop = 0; in SetCfgRfAgc()
847 u16 FeAgRegAgAgcSio = 0; in SetCfgRfAgc()
870 u16 Value; in ReadIFAgc()
930 u16 nBlocks; in DownloadMicrocode()
931 u16 BlockSize; in DownloadMicrocode()
938 pSrc += sizeof(u16); in DownloadMicrocode()
939 offset += sizeof(u16); in DownloadMicrocode()
941 pSrc += sizeof(u16); in DownloadMicrocode()
942 offset += sizeof(u16); in DownloadMicrocode()
950 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); in DownloadMicrocode()
951 pSrc += sizeof(u16); in DownloadMicrocode()
952 offset += sizeof(u16); in DownloadMicrocode()
956 pSrc += sizeof(u16); in DownloadMicrocode()
957 offset += sizeof(u16); in DownloadMicrocode()
961 pSrc += sizeof(u16); in DownloadMicrocode()
962 offset += sizeof(u16); in DownloadMicrocode()
975 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) in HI_Command()
978 u16 waitCmd; in HI_Command()
1062 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1079 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1085 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1100 u16 word;
1189 u16 AgModeLop = 0; in SetCfgPga()
1190 u16 AgModeHip = 0; in SetCfgPga()
1304 u16 curCmd; in SC_WaitForReady()
1315 static int SC_SendCommand(struct drxd_state *state, u16 cmd) in SC_SendCommand()
1318 u16 errCode; in SC_SendCommand()
1334 u16 subCmd, u16 param0, u16 param1) in SC_ProcStartCommand()
1337 u16 scExec; in SC_ProcStartCommand()
1358 u16 subCmd, u16 param0, u16 param1) in SC_SetPrefParamCommand()
1386 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1412 u16 EcOcRegIprInvMpg = 0; in ConfigureMPEGOutput()
1413 u16 EcOcRegOcModeLop = 0; in ConfigureMPEGOutput()
1414 u16 EcOcRegOcModeHip = 0; in ConfigureMPEGOutput()
1415 u16 EcOcRegOcMpgSio = 0; in ConfigureMPEGOutput()
1500 u16 deviceId = 0; in SetDeviceTypeId()
1645 oscClockDeviation = (u16) ((((s32) (sysClockFreq) - in CorrectSysClockDeviation()
1655 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1793 u16 rcControl; in StartDiversity()
1872 u16 beOptEna; in SetCfgNoiseCalibration()
1909 u16 transmissionParams = 0; in DRX_Start()
1910 u16 operationMode = 0; in DRX_Start()
1911 u16 qpskTdTpsPwr = 0; in DRX_Start()
1912 u16 qam16TdTpsPwr = 0; in DRX_Start()
1913 u16 qam64TdTpsPwr = 0; in DRX_Start()
1918 u16 qpskSnCeGain = 0; in DRX_Start()
1919 u16 qam16SnCeGain = 0; in DRX_Start()
1920 u16 qam64SnCeGain = 0; in DRX_Start()
1921 u16 qpskIsGainMan = 0; in DRX_Start()
1922 u16 qam16IsGainMan = 0; in DRX_Start()
1923 u16 qam64IsGainMan = 0; in DRX_Start()
1924 u16 qpskIsGainExp = 0; in DRX_Start()
1925 u16 qam16IsGainExp = 0; in DRX_Start()
1926 u16 qam64IsGainExp = 0; in DRX_Start()
1927 u16 bandwidthParam = 0; in DRX_Start()
2368 u16 sc_config; in DRX_Start()
2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2409 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2499 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2508 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2509 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2510 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2511 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2514 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2515 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2516 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2518 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2519 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2520 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2526 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2535 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2536 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2537 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2538 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2564 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2579 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2584 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2600 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2604 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2679 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2794 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength) in drxd_read_signal_strength()
2863 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr) in drxd_read_snr()