2104 	struct drxj_hi_cmd hi_cmd;  in drxj_dap_atomic_read_write_block()  local
2115 	hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;  in drxj_dap_atomic_read_write_block()
2116 	hi_cmd.param1 =  in drxj_dap_atomic_read_write_block()
2119 	hi_cmd.param2 =  in drxj_dap_atomic_read_write_block()
2121 	hi_cmd.param3 = (u16) ((datasize / 2) - 1);  in drxj_dap_atomic_read_write_block()
2123 		hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;  in drxj_dap_atomic_read_write_block()
2125 		hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;  in drxj_dap_atomic_read_write_block()
2126 	hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +  in drxj_dap_atomic_read_write_block()
2128 	hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);  in drxj_dap_atomic_read_write_block()
2142 	rc = hi_command(dev_addr, &hi_cmd, &dummy);  in drxj_dap_atomic_read_write_block()
2229 	struct drxj_hi_cmd hi_cmd;  in hi_cfg_command()  local
2235 	hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;  in hi_cfg_command()
2236 	hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;  in hi_cfg_command()
2237 	hi_cmd.param2 = ext_attr->hi_cfg_timing_div;  in hi_cfg_command()
2238 	hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;  in hi_cfg_command()
2239 	hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;  in hi_cfg_command()
2240 	hi_cmd.param5 = ext_attr->hi_cfg_ctrl;  in hi_cfg_command()
2241 	hi_cmd.param6 = ext_attr->hi_cfg_transmit;  in hi_cfg_command()
2243 	rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);  in hi_cfg_command()
3878 	struct drxj_hi_cmd hi_cmd;  in ctrl_i2c_bridge()  local
3885 	hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;  in ctrl_i2c_bridge()
3886 	hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;  in ctrl_i2c_bridge()
3888 		hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;  in ctrl_i2c_bridge()
3890 		hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;  in ctrl_i2c_bridge()
3892 	return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);  in ctrl_i2c_bridge()