Lines Matching refs:pll_prediv

696 				(pll->pll_prediv << 8) | (pll->pll_ratio << 0));  in dib8000_reset_pll()
727 				(pll->pll_prediv));  in dib8000_reset_pll()
746 	u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;  in dib8000_update_pll()
753 	if ((pll == NULL) || (pll->pll_prediv == prediv &&  in dib8000_update_pll()
757 …ediv: old =  %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->p…  in dib8000_update_pll()
766 				(pll->pll_prediv & 0x3f));  in dib8000_update_pll()
772 		internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;  in dib8000_update_pll()
792 …rediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);  in dib8000_update_pll()
794 			if (state->cfg.pll->pll_prediv != oldprediv) {  in dib8000_update_pll()
798 …or %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll-…  in dib8000_update_pll()
810 			dprintk("PLL: Update ratio (prediv: %d, ratio: %d)", state->cfg.pll->pll_prediv, ratio);  in dib8000_update_pll()
811 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL …  in dib8000_update_pll()