369 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)  in dib7000p_set_bandwidth()  argument
374 	state->current_bandwidth = bw;  in dib7000p_set_bandwidth()
378 		timf = state->cfg.bw->timf;  in dib7000p_set_bandwidth()
384 	timf = timf * (bw / 50) / 160;  in dib7000p_set_bandwidth()
445 	struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];  in dib7000p_reset_pll()  local
449 …dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio <…  in dib7000p_reset_pll()
454 		dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));  in dib7000p_reset_pll()
457 		clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |  in dib7000p_reset_pll()
458 …(bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw-…  in dib7000p_reset_pll()
463 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-…  in dib7000p_reset_pll()
464 		clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);  in dib7000p_reset_pll()
468 	dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));  in dib7000p_reset_pll()
469 	dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));  in dib7000p_reset_pll()
470 	dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));  in dib7000p_reset_pll()
471 	dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));  in dib7000p_reset_pll()
473 	dib7000p_write_word(state, 72, bw->sad_cfg);  in dib7000p_reset_pll()
485 static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)  in dib7000p_update_pll()  argument
496 	if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {  in dib7000p_update_pll()
497 …v: old =  %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ra…  in dib7000p_update_pll()
502 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f…  in dib7000p_update_pll()
507 		internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio;	/* new internal */  in dib7000p_update_pll()
806 	u32 dds = state->cfg.bw->ifreq & 0x1ffffff;  in dib7000p_set_dds()
807 	u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));  in dib7000p_set_dds()
937 	dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);  in dib7000p_update_timf()
1176 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)  in dib7000p_spur_protect()  argument
1198 	u32 xtal = state->cfg.bw->xtal_hz / 1000;  in dib7000p_spur_protect()
1202 	int bw_khz = bw;  in dib7000p_spur_protect()