312 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)  in dib7000m_set_bandwidth()  argument
316 	if (!bw)  in dib7000m_set_bandwidth()
317 		bw = 8000;  in dib7000m_set_bandwidth()
320 	state->current_bandwidth = bw;  in dib7000m_set_bandwidth()
330 	timf = timf * (bw / 50) / 160;  in dib7000m_set_bandwidth()
378 … dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)  in dib7000m_reset_pll_common()  argument
380 	dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));  in dib7000m_reset_pll_common()
381 	dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000)        & 0xffff));  in dib7000m_reset_pll_common()
382 	dib7000m_write_word(state, 21, (u16) ( (bw->ifreq          >> 16) & 0xffff));  in dib7000m_reset_pll_common()
383 	dib7000m_write_word(state, 22, (u16) (  bw->ifreq                 & 0xffff));  in dib7000m_reset_pll_common()
385 	dib7000m_write_word(state, 928, bw->sad_cfg);  in dib7000m_reset_pll_common()
390 	const struct dibx000_bandwidth_config *bw = state->cfg.bw;  in dib7000m_reset_pll()  local
394 	reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) |  in dib7000m_reset_pll()
395 		(bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) |  in dib7000m_reset_pll()
396 		(bw->enable_refdiv << 1) | (0 << 0);  in dib7000m_reset_pll()
397 	reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;  in dib7000m_reset_pll()
410 		reg_907 |= (bw->pll_ratio & 0x3f) << 9;  in dib7000m_reset_pll()
411 		reg_910 |= (bw->pll_prediv << 5);  in dib7000m_reset_pll()
418 	dib7000m_reset_pll_common(state, bw);  in dib7000m_reset_pll()
423 	const struct dibx000_bandwidth_config *bw = state->cfg.bw;  in dib7000mc_reset_pll()  local
427 	dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));  in dib7000mc_reset_pll()
432 			(bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |  in dib7000mc_reset_pll()
433 			(1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0);  in dib7000mc_reset_pll()
435 	clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3);  in dib7000mc_reset_pll()
439 	dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));  in dib7000mc_reset_pll()
441 	dib7000m_reset_pll_common(state, bw);  in dib7000mc_reset_pll()
622 	state->internal_clk = state->cfg.bw->internal;  in dib7000m_demod_reset()
1415 	st->timf_default = cfg->bw->timf;  in dib7000m_attach()