331 …ARD_RESET(state) do {  if (cfg->reset) {  if (cfg->sleep) cfg->sleep(fe, 0); msleep(10);  cfg->res…
525 static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)  in dib0090_reset_digital()  argument
532 	if (cfg->in_soc)  in dib0090_reset_digital()
537 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <…  in dib0090_reset_digital()
538 	if (cfg->clkoutdrive != 0)  in dib0090_reset_digital()
539 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | …  in dib0090_reset_digital()
540 				| (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));  in dib0090_reset_digital()
542 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | …  in dib0090_reset_digital()
543 				| (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));  in dib0090_reset_digital()
549 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_reset_digital()
550 			&& !cfg->io.pll_bypass) {  in dib0090_reset_digital()
561 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_reset_digital()
586 	if (cfg->io.pll_bypass) {  in dib0090_reset_digital()
587 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_reset_digital()
592 static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)  in dib0090_fw_reset_digital()  argument
606 …((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) …  in dib0090_fw_reset_digital()
608 …v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | …  in dib0090_fw_reset_digital()
609 	if (cfg->clkoutdrive != 0)  in dib0090_fw_reset_digital()
610 		v |= cfg->clkoutdrive << 5;  in dib0090_fw_reset_digital()
621 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_fw_reset_digital()
632 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_fw_reset_digital()
657 	if (cfg->io.pll_bypass) {  in dib0090_fw_reset_digital()
658 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_fw_reset_digital()
1036 static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_rframp()  argument
1038 	state->rf_ramp = cfg;  in dib0090_set_rframp()
1041 static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_rframp_pwm()  argument
1043 	state->rf_ramp = cfg;  in dib0090_set_rframp_pwm()
1047 	dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a));  in dib0090_set_rframp_pwm()
1049 	dib0090_write_regs(state, 0x2c, cfg + 3, 6);  in dib0090_set_rframp_pwm()
1050 	dib0090_write_regs(state, 0x3e, cfg + 9, 2);  in dib0090_set_rframp_pwm()
1053 static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_bbramp()  argument
1055 	state->bb_ramp = cfg;  in dib0090_set_bbramp()
1056 	dib0090_set_boost(state, cfg[0] > 500);	/* we want the boost if the gain is higher that 50dB */  in dib0090_set_bbramp()
1059 static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_bbramp_pwm()  argument
1061 	state->bb_ramp = cfg;  in dib0090_set_bbramp_pwm()
1063 	dib0090_set_boost(state, cfg[0] > 500);	/* we want the boost if the gain is higher that 50dB */  in dib0090_set_bbramp_pwm()
1066 	dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33));  in dib0090_set_bbramp_pwm()
1067 	dib0090_write_regs(state, 0x35, cfg + 3, 4);  in dib0090_set_bbramp_pwm()