117 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)  in dib0070_write_reg()  function
167     dib0070_write_reg(state, 0x02, tmp);  in dib0070_set_bandwidth()
173 	dib0070_write_reg(state, 0x17, value & 0xfffc);  in dib0070_set_bandwidth()
175 	dib0070_write_reg(state, 0x01, tmp | (60 << 9));  in dib0070_set_bandwidth()
177 	dib0070_write_reg(state, 0x17, value);  in dib0070_set_bandwidth()
190 		dib0070_write_reg(state, 0x0f, 0xed10);  in dib0070_captrim()
191 		dib0070_write_reg(state, 0x17,    0x0034);  in dib0070_captrim()
193 		dib0070_write_reg(state, 0x18, 0x0032);  in dib0070_captrim()
201 		dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);  in dib0070_captrim()
235 		dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);  in dib0070_captrim()
236 		dib0070_write_reg(state, 0x18, 0x07ff);  in dib0070_captrim()
248 	return dib0070_write_reg(state, 0x15, lo5);  in dib0070_set_ctrl_lo5()
256 		dib0070_write_reg(state, 0x1b, 0xff00);  in dib0070_ctrl_agc_filter()
257 		dib0070_write_reg(state, 0x1a, 0x0000);  in dib0070_ctrl_agc_filter()
259 		dib0070_write_reg(state, 0x1b, 0x4112);  in dib0070_ctrl_agc_filter()
261 		dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);  in dib0070_ctrl_agc_filter()
264 		dib0070_write_reg(state, 0x1a, 0x0009);  in dib0070_ctrl_agc_filter()
396 		dib0070_write_reg(state, 0x17, 0x30);  in dib0070_tune_digital()
448 		dib0070_write_reg(state, 0x11, (u16)FBDiv);  in dib0070_tune_digital()
449 		dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);  in dib0070_tune_digital()
450 		dib0070_write_reg(state, 0x13, (u16) Rest);  in dib0070_tune_digital()
456 				dib0070_write_reg(state, 0x1d, 0xFFFF);  in dib0070_tune_digital()
461 		dib0070_write_reg(state, 0x20,  in dib0070_tune_digital()
485 		dib0070_write_reg(state, 0x0f,  in dib0070_tune_digital()
491 			dib0070_write_reg(state, 0x0f,  in dib0070_tune_digital()
497 	dib0070_write_reg(state, 0x06, 0x3fff);  in dib0070_tune_digital()
498 		dib0070_write_reg(state, 0x07,  in dib0070_tune_digital()
500 	dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));  in dib0070_tune_digital()
501 	dib0070_write_reg(state, 0x0d, 0x0d80);  in dib0070_tune_digital()
504 	dib0070_write_reg(state, 0x18,   0x07ff);  in dib0070_tune_digital()
505 	dib0070_write_reg(state, 0x17, 0x0033);  in dib0070_tune_digital()
568 	return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));  in dib0070_set_rf_output()
616     dib0070_write_reg(state, 0x18, 0x07ff);  in dib0070_read_wbd_offset()
617 …dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x00…  in dib0070_read_wbd_offset()
618 …dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0…  in dib0070_read_wbd_offset()
621     dib0070_write_reg(state, 0x20, tuner_en);  in dib0070_read_wbd_offset()
682 			dib0070_write_reg(state, (u8)r, pgm_read_word(n++));  in dib0070_reset()
698 	dib0070_write_reg(state, 0x10, r);  in dib0070_reset()
699 	dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));  in dib0070_reset()
703 		dib0070_write_reg(state, 0x02, r | (1 << 5));  in dib0070_reset()
711 	dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);  in dib0070_reset()