Lines Matching refs:cfg
114 struct _iohandle cfg; member
286 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); in diva_irq()
304 val = readb(hw->cfg.p); in diva20x_irq()
311 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */ in diva20x_irq()
323 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); in tiger_irq()
341 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); in elsa_irq()
359 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
364 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
410 writel(PITA_INT0_ENABLE, hw->cfg.p); in enable_hwirq()
414 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in enable_hwirq()
417 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
420 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
423 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
425 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
428 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
430 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
434 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
438 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
454 writel(0, hw->cfg.p); in disable_hwirq()
458 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in disable_hwirq()
461 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
464 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
467 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
469 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
472 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
474 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
478 outb(0, (u32)hw->cfg.start + GAZEL_INCSR); in disable_hwirq()
507 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
509 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
512 outb(9, (u32)hw->cfg.start + 0x69); in reset_inf()
514 (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
518 hw->cfg.p + PITA_MISC_REG); in reset_inf()
520 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG); in reset_inf()
525 hw->cfg.p + PITA_MISC_REG); in reset_inf()
528 hw->cfg.p + PITA_MISC_REG); in reset_inf()
548 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
550 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
552 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
554 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
558 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
563 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
570 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
572 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
575 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
647 if (hw->cfg.mode) { in release_io()
648 if (hw->cfg.p) { in release_io()
649 release_mem_region(hw->cfg.start, hw->cfg.size); in release_io()
650 iounmap(hw->cfg.p); in release_io()
652 release_region(hw->cfg.start, hw->cfg.size); in release_io()
653 hw->cfg.mode = AM_NONE; in release_io()
671 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar); in setup_io()
672 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar); in setup_io()
674 if (!request_mem_region(hw->cfg.start, hw->cfg.size, in setup_io()
678 if (!request_region(hw->cfg.start, hw->cfg.size, in setup_io()
685 (ulong)hw->cfg.start, (ulong)hw->cfg.size); in setup_io()
689 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size); in setup_io()
690 hw->cfg.mode = hw->ci->cfg_mode; in setup_io()
693 hw->name, (ulong)hw->cfg.start, in setup_io()
694 (ulong)hw->cfg.size, hw->ci->cfg_mode); in setup_io()
729 hw->isac.mode = hw->cfg.mode; in setup_io()
730 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE; in setup_io()
731 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT; in setup_io()
732 hw->hscx.mode = hw->cfg.mode; in setup_io()
733 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; in setup_io()
734 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; in setup_io()
755 hw->isac.mode = hw->cfg.mode; in setup_io()
756 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
757 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
758 hw->hscx.mode = hw->cfg.mode; in setup_io()
759 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
760 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
761 outb(0xff, (ulong)hw->cfg.start); in setup_io()
763 outb(0x00, (ulong)hw->cfg.start); in setup_io()
765 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL); in setup_io()