Lines Matching refs:parent_irq
53 unsigned long parent_irq; member
101 parent_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c_irq_mask()
109 irq_data->parent_irq); in s3c_irq_mask()
129 irq_data->parent_irq); in s3c_irq_unmask()
475 if (irq_data->parent_irq > 31) { in s3c24xx_irq_map()
477 irq_data->parent_irq); in s3c24xx_irq_map()
481 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_map()
487 irq_data->parent_irq); in s3c24xx_irq_map()
490 irq_data->parent_irq); in s3c24xx_irq_map()
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
633 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
634 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
635 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
636 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
637 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
638 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
639 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
640 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
641 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
642 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
643 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
692 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
693 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
765 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
766 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
767 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
768 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
769 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
770 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
771 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
772 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
773 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
774 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
775 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
788 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
789 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
792 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
793 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
863 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
864 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
872 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
873 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
874 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
875 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
876 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
877 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
878 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
879 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
880 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
881 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
882 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
961 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
962 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
963 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
964 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
965 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
966 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
967 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
968 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
969 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
970 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
971 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1033 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1034 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1035 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1036 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1037 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1038 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1039 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1040 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1041 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1042 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1043 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1044 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1115 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1116 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1124 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1125 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1126 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1127 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1128 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1129 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1130 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1131 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1132 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1133 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1134 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1213 irq_data->parent_irq = intspec[1]; in s3c24xx_irq_xlate_of()
1214 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_xlate_of()