Lines Matching refs:p
72 struct intc_irqpin_priv *p; member
112 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, in intc_irqpin_read() argument
115 struct intc_irqpin_iomem *i = &p->iomem[reg]; in intc_irqpin_read()
120 static inline void intc_irqpin_write(struct intc_irqpin_priv *p, in intc_irqpin_write() argument
123 struct intc_irqpin_iomem *i = &p->iomem[reg]; in intc_irqpin_write()
128 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, in intc_irqpin_hwirq_mask() argument
131 return BIT((p->iomem[reg].width - 1) - hw_irq); in intc_irqpin_hwirq_mask()
134 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, in intc_irqpin_irq_write_hwirq() argument
137 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); in intc_irqpin_irq_write_hwirq()
142 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, in intc_irqpin_read_modify_write() argument
151 tmp = intc_irqpin_read(p, reg); in intc_irqpin_read_modify_write()
154 intc_irqpin_write(p, reg, tmp); in intc_irqpin_read_modify_write()
159 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, in intc_irqpin_mask_unmask_prio() argument
166 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, in intc_irqpin_mask_unmask_prio()
171 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) in intc_irqpin_set_sense() argument
174 int bitfield_width = p->config.sense_bitfield_width; in intc_irqpin_set_sense()
177 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); in intc_irqpin_set_sense()
182 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, in intc_irqpin_set_sense()
189 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", in intc_irqpin_dbg()
195 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_irq_enable() local
198 intc_irqpin_dbg(&p->irq[hw_irq], "enable"); in intc_irqpin_irq_enable()
199 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); in intc_irqpin_irq_enable()
204 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_irq_disable() local
207 intc_irqpin_dbg(&p->irq[hw_irq], "disable"); in intc_irqpin_irq_disable()
208 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); in intc_irqpin_irq_disable()
213 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_shared_irq_enable() local
216 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); in intc_irqpin_shared_irq_enable()
217 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); in intc_irqpin_shared_irq_enable()
219 p->shared_irq_mask &= ~BIT(hw_irq); in intc_irqpin_shared_irq_enable()
224 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_shared_irq_disable() local
227 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); in intc_irqpin_shared_irq_disable()
228 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); in intc_irqpin_shared_irq_disable()
230 p->shared_irq_mask |= BIT(hw_irq); in intc_irqpin_shared_irq_disable()
235 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_irq_enable_force() local
236 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; in intc_irqpin_irq_enable_force()
249 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_irq_disable_force() local
250 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; in intc_irqpin_irq_disable_force()
274 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_irq_set_type() local
279 return intc_irqpin_set_sense(p, irqd_to_hwirq(d), in intc_irqpin_irq_set_type()
285 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); in intc_irqpin_irq_set_wake() local
287 if (!p->clk) in intc_irqpin_irq_set_wake()
291 clk_enable(p->clk); in intc_irqpin_irq_set_wake()
293 clk_disable(p->clk); in intc_irqpin_irq_set_wake()
301 struct intc_irqpin_priv *p = i->p; in intc_irqpin_irq_handler() local
305 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); in intc_irqpin_irq_handler()
307 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { in intc_irqpin_irq_handler()
308 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); in intc_irqpin_irq_handler()
318 struct intc_irqpin_priv *p = dev_id; in intc_irqpin_shared_irq_handler() local
319 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); in intc_irqpin_shared_irq_handler()
325 if (BIT(k) & p->shared_irq_mask) in intc_irqpin_shared_irq_handler()
328 status |= intc_irqpin_irq_handler(irq, &p->irq[k]); in intc_irqpin_shared_irq_handler()
338 struct intc_irqpin_priv *p = h->host_data; in intc_irqpin_irq_domain_map() local
340 p->irq[hw].domain_irq = virq; in intc_irqpin_irq_domain_map()
341 p->irq[hw].hw_irq = hw; in intc_irqpin_irq_domain_map()
343 intc_irqpin_dbg(&p->irq[hw], "map"); in intc_irqpin_irq_domain_map()
345 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); in intc_irqpin_irq_domain_map()
372 struct intc_irqpin_priv *p; in intc_irqpin_probe() local
384 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); in intc_irqpin_probe()
385 if (!p) { in intc_irqpin_probe()
392 memcpy(&p->config, pdata, sizeof(*pdata)); in intc_irqpin_probe()
395 &p->config.sense_bitfield_width); in intc_irqpin_probe()
396 p->config.control_parent = of_property_read_bool(dev->of_node, in intc_irqpin_probe()
399 if (!p->config.sense_bitfield_width) in intc_irqpin_probe()
400 p->config.sense_bitfield_width = 4; /* default to 4 bits */ in intc_irqpin_probe()
402 p->pdev = pdev; in intc_irqpin_probe()
403 platform_set_drvdata(pdev, p); in intc_irqpin_probe()
405 p->clk = devm_clk_get(dev, NULL); in intc_irqpin_probe()
406 if (IS_ERR(p->clk)) { in intc_irqpin_probe()
408 p->clk = NULL; in intc_irqpin_probe()
431 p->irq[k].p = p; in intc_irqpin_probe()
432 p->irq[k].requested_irq = irq->start; in intc_irqpin_probe()
435 p->number_of_irqs = k; in intc_irqpin_probe()
436 if (p->number_of_irqs < 1) { in intc_irqpin_probe()
444 i = &p->iomem[k]; in intc_irqpin_probe()
482 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM, in intc_irqpin_probe()
490 for (k = 0; k < p->number_of_irqs; k++) in intc_irqpin_probe()
491 intc_irqpin_mask_unmask_prio(p, k, 1); in intc_irqpin_probe()
494 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); in intc_irqpin_probe()
497 ref_irq = p->irq[0].requested_irq; in intc_irqpin_probe()
498 p->shared_irqs = true; in intc_irqpin_probe()
499 for (k = 1; k < p->number_of_irqs; k++) { in intc_irqpin_probe()
500 if (ref_irq != p->irq[k].requested_irq) { in intc_irqpin_probe()
501 p->shared_irqs = false; in intc_irqpin_probe()
507 if (p->config.control_parent) { in intc_irqpin_probe()
510 } else if (!p->shared_irqs) { in intc_irqpin_probe()
518 irq_chip = &p->irq_chip; in intc_irqpin_probe()
526 p->irq_domain = irq_domain_add_simple(dev->of_node, in intc_irqpin_probe()
527 p->number_of_irqs, in intc_irqpin_probe()
528 p->config.irq_base, in intc_irqpin_probe()
529 &intc_irqpin_irq_domain_ops, p); in intc_irqpin_probe()
530 if (!p->irq_domain) { in intc_irqpin_probe()
536 if (p->shared_irqs) { in intc_irqpin_probe()
538 if (devm_request_irq(dev, p->irq[0].requested_irq, in intc_irqpin_probe()
540 IRQF_SHARED, name, p)) { in intc_irqpin_probe()
547 for (k = 0; k < p->number_of_irqs; k++) { in intc_irqpin_probe()
548 if (devm_request_irq(dev, p->irq[k].requested_irq, in intc_irqpin_probe()
550 &p->irq[k])) { in intc_irqpin_probe()
559 for (k = 0; k < p->number_of_irqs; k++) in intc_irqpin_probe()
560 intc_irqpin_mask_unmask_prio(p, k, 0); in intc_irqpin_probe()
562 dev_info(dev, "driving %d irqs\n", p->number_of_irqs); in intc_irqpin_probe()
565 if (p->config.irq_base) { in intc_irqpin_probe()
566 if (p->config.irq_base != p->irq[0].domain_irq) in intc_irqpin_probe()
568 p->config.irq_base, p->irq[0].domain_irq); in intc_irqpin_probe()
574 irq_domain_remove(p->irq_domain); in intc_irqpin_probe()
583 struct intc_irqpin_priv *p = platform_get_drvdata(pdev); in intc_irqpin_remove() local
585 irq_domain_remove(p->irq_domain); in intc_irqpin_remove()