66 	iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr);  in ipoctal_reset_channel()
68 	iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr);  in ipoctal_reset_channel()
69 	iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr);  in ipoctal_reset_channel()
70 	iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr);  in ipoctal_reset_channel()
71 	iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr);  in ipoctal_reset_channel()
84 	iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);  in ipoctal_port_activate()
162 			iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr);  in ipoctal_irq_rx()
205 	iowrite8(value, &channel->regs->w.thr);  in ipoctal_irq_tx()
223 		iowrite8(CR_CMD_RESET_BREAK_CHANGE, &channel->regs->w.cr);  in ipoctal_irq_channel()
226 		iowrite8(CR_DISABLE_TX, &channel->regs->w.cr);  in ipoctal_irq_channel()
230 			iowrite8(CR_CMD_NEGATE_RTSN, &channel->regs->w.cr);  in ipoctal_irq_channel()
231 			iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);  in ipoctal_irq_channel()
335 			 &channel->regs->w.mr); /* mr1 */  in ipoctal_inst_slot()
336 		iowrite8(0, &channel->regs->w.mr); /* mr2 */  in ipoctal_inst_slot()
337 		iowrite8(TX_CLK_9600  | RX_CLK_9600, &channel->regs->w.csr);  in ipoctal_inst_slot()
341 		iowrite8(ACR_BRG_SET2, &block_regs[i].w.acr);  in ipoctal_inst_slot()
343 			 &block_regs[i].w.opcr);  in ipoctal_inst_slot()
346 			 &block_regs[i].w.imr);  in ipoctal_inst_slot()
453 		iowrite8(CR_DISABLE_RX, &channel->regs->w.cr);  in ipoctal_write_tty()
455 		iowrite8(CR_CMD_ASSERT_RTSN, &channel->regs->w.cr);  in ipoctal_write_tty()
462 	iowrite8(CR_ENABLE_TX, &channel->regs->w.cr);  in ipoctal_write_tty()
606 	iowrite8(mr1, &channel->regs->w.mr);  in ipoctal_set_termios()
607 	iowrite8(mr2, &channel->regs->w.mr);  in ipoctal_set_termios()
608 	iowrite8(csr, &channel->regs->w.csr);  in ipoctal_set_termios()
612 		iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);  in ipoctal_set_termios()