532 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in __arm_smmu_tlb_sync()  local
534 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);  in __arm_smmu_tlb_sync()
535 	while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)  in __arm_smmu_tlb_sync()
698 	void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);  in arm_smmu_global_fault()  local
700 	gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);  in arm_smmu_global_fault()
701 	gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);  in arm_smmu_global_fault()
702 	gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);  in arm_smmu_global_fault()
703 	gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);  in arm_smmu_global_fault()
714 	writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);  in arm_smmu_global_fault()
725 	void __iomem *cb_base, *gr0_base, *gr1_base;  in arm_smmu_init_context_bank()  local
727 	gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_init_context_bank()
1010 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_master_configure_smrs()  local
1045 		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));  in arm_smmu_master_configure_smrs()
1062 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_master_free_smrs()  local
1072 		writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));  in arm_smmu_master_free_smrs()
1085 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_domain_add_master()  local
1098 		writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));  in arm_smmu_domain_add_master()
1109 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_domain_remove_master()  local
1123 			       gr0_base + ARM_SMMU_GR0_S2CR(idx));  in arm_smmu_domain_remove_master()
1463 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_device_reset()  local
1474 		writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));  in arm_smmu_device_reset()
1476 			gr0_base + ARM_SMMU_GR0_S2CR(i));  in arm_smmu_device_reset()
1487 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);  in arm_smmu_device_reset()
1488 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);  in arm_smmu_device_reset()
1534 	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);  in arm_smmu_device_cfg_probe()  local
1541 	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);  in arm_smmu_device_cfg_probe()
1594 		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));  in arm_smmu_device_cfg_probe()
1595 		smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));  in arm_smmu_device_cfg_probe()
1615 	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);  in arm_smmu_device_cfg_probe()
1636 	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);  in arm_smmu_device_cfg_probe()