274 	struct arm_smmu_master_cfg	cfg;  member
323 #define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)  argument
324 #define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)  argument
336 	struct arm_smmu_cfg		cfg;  member
413 	struct arm_smmu_master_cfg *cfg = NULL;  in find_smmu_master_cfg()  local
417 		cfg = iommu_group_get_iommudata(group);  in find_smmu_master_cfg()
421 	return cfg;  in find_smmu_master_cfg()
476 	master->cfg.num_streamids	= masterspec->args_count;  in register_smmu_master()
478 	for (i = 0; i < master->cfg.num_streamids; ++i) {  in register_smmu_master()
488 		master->cfg.streamids[i] = streamid;  in register_smmu_master()
556 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_tlb_inv_context()  local
558 	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;  in arm_smmu_tlb_inv_context()
562 		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_tlb_inv_context()
563 		writel_relaxed(ARM_SMMU_CB_ASID(cfg),  in arm_smmu_tlb_inv_context()
567 		writel_relaxed(ARM_SMMU_CB_VMID(cfg),  in arm_smmu_tlb_inv_context()
578 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_tlb_inv_range_nosync()  local
580 	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;  in arm_smmu_tlb_inv_range_nosync()
584 		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_tlb_inv_range_nosync()
589 			iova |= ARM_SMMU_CB_ASID(cfg);  in arm_smmu_tlb_inv_range_nosync()
594 			iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;  in arm_smmu_tlb_inv_range_nosync()
600 		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_tlb_inv_range_nosync()
607 		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);  in arm_smmu_tlb_inv_range_nosync()
648 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_context_fault()  local
652 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_context_fault()
679 		    iova, fsynr, cfg->cbndx);  in arm_smmu_context_fault()
723 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_init_context_bank()  local
729 	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;  in arm_smmu_init_context_bank()
730 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_init_context_bank()
743 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));  in arm_smmu_init_context_bank()
747 	reg = cfg->cbar;  in arm_smmu_init_context_bank()
749 		reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;  in arm_smmu_init_context_bank()
759 		reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;  in arm_smmu_init_context_bank()
761 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));  in arm_smmu_init_context_bank()
768 		reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;  in arm_smmu_init_context_bank()
774 		reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;  in arm_smmu_init_context_bank()
824 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_init_domain_context()  local
855 		cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;  in arm_smmu_init_domain_context()
870 		cfg->cbar = CBAR_TYPE_S2_TRANS;  in arm_smmu_init_domain_context()
889 	cfg->cbndx = ret;  in arm_smmu_init_domain_context()
891 		cfg->irptndx = atomic_inc_return(&smmu->irptndx);  in arm_smmu_init_domain_context()
892 		cfg->irptndx %= smmu->num_context_irqs;  in arm_smmu_init_domain_context()
894 		cfg->irptndx = cfg->cbndx;  in arm_smmu_init_domain_context()
921 	irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];  in arm_smmu_init_domain_context()
926 			cfg->irptndx, irq);  in arm_smmu_init_domain_context()
927 		cfg->irptndx = INVALID_IRPTNDX;  in arm_smmu_init_domain_context()
947 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_destroy_domain_context()  local
958 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_destroy_domain_context()
961 	if (cfg->irptndx != INVALID_IRPTNDX) {  in arm_smmu_destroy_domain_context()
962 		irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];  in arm_smmu_destroy_domain_context()
969 	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);  in arm_smmu_destroy_domain_context()
1006 					  struct arm_smmu_master_cfg *cfg)  in arm_smmu_master_configure_smrs()  argument
1015 	if (cfg->smrs)  in arm_smmu_master_configure_smrs()
1018 	smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);  in arm_smmu_master_configure_smrs()
1021 			cfg->num_streamids);  in arm_smmu_master_configure_smrs()
1026 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_master_configure_smrs()
1037 			.id	= cfg->streamids[i],  in arm_smmu_master_configure_smrs()
1042 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_master_configure_smrs()
1048 	cfg->smrs = smrs;  in arm_smmu_master_configure_smrs()
1059 				      struct arm_smmu_master_cfg *cfg)  in arm_smmu_master_free_smrs()  argument
1063 	struct arm_smmu_smr *smrs = cfg->smrs;  in arm_smmu_master_free_smrs()
1069 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_master_free_smrs()
1076 	cfg->smrs = NULL;  in arm_smmu_master_free_smrs()
1081 				      struct arm_smmu_master_cfg *cfg)  in arm_smmu_domain_add_master()  argument
1088 	ret = arm_smmu_master_configure_smrs(smmu, cfg);  in arm_smmu_domain_add_master()
1092 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_domain_add_master()
1095 		idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];  in arm_smmu_domain_add_master()
1097 		       (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);  in arm_smmu_domain_add_master()
1105 					  struct arm_smmu_master_cfg *cfg)  in arm_smmu_domain_remove_master()  argument
1112 	if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)  in arm_smmu_domain_remove_master()
1119 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_domain_remove_master()
1120 		u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];  in arm_smmu_domain_remove_master()
1126 	arm_smmu_master_free_smrs(smmu, cfg);  in arm_smmu_domain_remove_master()
1134 	struct arm_smmu_master_cfg *cfg;  in arm_smmu_attach_dev()  local
1164 	cfg = find_smmu_master_cfg(dev);  in arm_smmu_attach_dev()
1165 	if (!cfg)  in arm_smmu_attach_dev()
1168 	ret = arm_smmu_domain_add_master(smmu_domain, cfg);  in arm_smmu_attach_dev()
1177 	struct arm_smmu_master_cfg *cfg;  in arm_smmu_detach_dev()  local
1179 	cfg = find_smmu_master_cfg(dev);  in arm_smmu_detach_dev()
1180 	if (!cfg)  in arm_smmu_detach_dev()
1184 	arm_smmu_domain_remove_master(smmu_domain, cfg);  in arm_smmu_detach_dev()
1226 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_iova_to_phys_hard()  local
1233 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_iova_to_phys_hard()
1323 	struct arm_smmu_master_cfg *cfg;  in arm_smmu_add_pci_device()  local
1329 	cfg = iommu_group_get_iommudata(group);  in arm_smmu_add_pci_device()
1330 	if (!cfg) {  in arm_smmu_add_pci_device()
1331 		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);  in arm_smmu_add_pci_device()
1332 		if (!cfg) {  in arm_smmu_add_pci_device()
1337 		iommu_group_set_iommudata(group, cfg,  in arm_smmu_add_pci_device()
1341 	if (cfg->num_streamids >= MAX_MASTER_STREAMIDS) {  in arm_smmu_add_pci_device()
1351 	for (i = 0; i < cfg->num_streamids; ++i)  in arm_smmu_add_pci_device()
1352 		if (cfg->streamids[i] == sid)  in arm_smmu_add_pci_device()
1356 	if (i == cfg->num_streamids)  in arm_smmu_add_pci_device()
1357 		cfg->streamids[cfg->num_streamids++] = sid;  in arm_smmu_add_pci_device()
1383 	iommu_group_set_iommudata(group, &master->cfg, NULL);  in arm_smmu_add_platform_device()