650 	void __iomem *cb_base;  in arm_smmu_context_fault()  local
652 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_context_fault()
653 	fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_context_fault()
663 	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);  in arm_smmu_context_fault()
666 	far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);  in arm_smmu_context_fault()
669 	far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);  in arm_smmu_context_fault()
685 	writel(fsr, cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_context_fault()
689 		writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);  in arm_smmu_context_fault()
725 	void __iomem *cb_base, *gr0_base, *gr1_base;  in arm_smmu_init_context_bank()  local
730 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_init_context_bank()
766 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);  in arm_smmu_init_context_bank()
769 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);  in arm_smmu_init_context_bank()
772 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);  in arm_smmu_init_context_bank()
775 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);  in arm_smmu_init_context_bank()
778 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);  in arm_smmu_init_context_bank()
780 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);  in arm_smmu_init_context_bank()
786 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
790 			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);  in arm_smmu_init_context_bank()
794 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
800 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);  in arm_smmu_init_context_bank()
802 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);  in arm_smmu_init_context_bank()
812 	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_init_context_bank()
948 	void __iomem *cb_base;  in arm_smmu_destroy_domain_context()  local
958 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_destroy_domain_context()
959 	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_destroy_domain_context()
1229 	void __iomem *cb_base;  in arm_smmu_iova_to_phys_hard()  local
1233 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_iova_to_phys_hard()
1237 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);  in arm_smmu_iova_to_phys_hard()
1240 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);  in arm_smmu_iova_to_phys_hard()
1242 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);  in arm_smmu_iova_to_phys_hard()
1245 	if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,  in arm_smmu_iova_to_phys_hard()
1253 	phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);  in arm_smmu_iova_to_phys_hard()
1254 	phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;  in arm_smmu_iova_to_phys_hard()
1464 	void __iomem *cb_base;  in arm_smmu_device_reset()  local
1481 		cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);  in arm_smmu_device_reset()
1482 		writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_device_reset()
1483 		writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_device_reset()