140 	u16 dig1 = 0, dig2 = WM97XX_RPR;  in wm9705_phy_init()  local
167 	dig1 &= 0xff0f;  in wm9705_phy_init()
168 	dig1 |= WM97XX_DELAY(delay);  in wm9705_phy_init()
179 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1);  in wm9705_phy_init()
301 	u16 dig1, dig2;  in wm9705_acc_enable()  local
304 	dig1 = wm->dig[1];  in wm9705_acc_enable()
312 		dig1 &= ~(WM97XX_CM_RATE_MASK | WM97XX_ADCSEL_MASK |  in wm9705_acc_enable()
314 		dig1 |= WM97XX_CTC | WM97XX_COO | WM97XX_SLEN |  in wm9705_acc_enable()
319 			dig1 |= WM97XX_ADCSEL_PRES;  in wm9705_acc_enable()
322 		dig1 &= ~(WM97XX_CTC | WM97XX_COO | WM97XX_SLEN);  in wm9705_acc_enable()
328 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1);  in wm9705_acc_enable()