Lines Matching refs:dd
135 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, in qib_pcie_ddinit() argument
141 dd->pcidev = pdev; in qib_pcie_ddinit()
142 pci_set_drvdata(pdev, dd); in qib_pcie_ddinit()
149 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU); in qib_pcie_ddinit()
151 dd->kregbase = ioremap_nocache(addr, len); in qib_pcie_ddinit()
154 if (!dd->kregbase) in qib_pcie_ddinit()
157 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); in qib_pcie_ddinit()
158 dd->physaddr = addr; /* used for io_remap, etc. */ in qib_pcie_ddinit()
164 dd->pcibar0 = addr; in qib_pcie_ddinit()
165 dd->pcibar1 = addr >> 32; in qib_pcie_ddinit()
166 dd->deviceid = ent->device; /* save for later use */ in qib_pcie_ddinit()
167 dd->vendorid = ent->vendor; in qib_pcie_ddinit()
177 void qib_pcie_ddcleanup(struct qib_devdata *dd) in qib_pcie_ddcleanup() argument
179 u64 __iomem *base = (void __iomem *) dd->kregbase; in qib_pcie_ddcleanup()
181 dd->kregbase = NULL; in qib_pcie_ddcleanup()
183 if (dd->piobase) in qib_pcie_ddcleanup()
184 iounmap(dd->piobase); in qib_pcie_ddcleanup()
185 if (dd->userbase) in qib_pcie_ddcleanup()
186 iounmap(dd->userbase); in qib_pcie_ddcleanup()
187 if (dd->piovl15base) in qib_pcie_ddcleanup()
188 iounmap(dd->piovl15base); in qib_pcie_ddcleanup()
190 pci_disable_device(dd->pcidev); in qib_pcie_ddcleanup()
191 pci_release_regions(dd->pcidev); in qib_pcie_ddcleanup()
193 pci_set_drvdata(dd->pcidev, NULL); in qib_pcie_ddcleanup()
196 static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt, in qib_msix_setup() argument
204 ret = pci_msix_vec_count(dd->pcidev); in qib_msix_setup()
220 ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec); in qib_msix_setup()
238 dd, in qib_msix_setup()
242 qib_enable_intx(dd->pcidev); in qib_msix_setup()
250 static int qib_msi_setup(struct qib_devdata *dd, int pos) in qib_msi_setup() argument
252 struct pci_dev *pdev = dd->pcidev; in qib_msi_setup()
258 qib_dev_err(dd, in qib_msi_setup()
264 &dd->msi_lo); in qib_msi_setup()
266 &dd->msi_hi); in qib_msi_setup()
271 &dd->msi_data); in qib_msi_setup()
275 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent, in qib_pcie_params() argument
281 if (!pci_is_pcie(dd->pcidev)) { in qib_pcie_params()
282 qib_dev_err(dd, "Can't find PCI Express capability!\n"); in qib_pcie_params()
284 dd->lbus_width = 1; in qib_pcie_params()
285 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ in qib_pcie_params()
289 pos = dd->pcidev->msix_cap; in qib_pcie_params()
291 qib_msix_setup(dd, pos, nent, entry); in qib_pcie_params()
294 pos = dd->pcidev->msi_cap; in qib_pcie_params()
296 ret = qib_msi_setup(dd, pos); in qib_pcie_params()
298 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n"); in qib_pcie_params()
301 qib_enable_intx(dd->pcidev); in qib_pcie_params()
303 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in qib_pcie_params()
311 dd->lbus_width = linkstat; in qib_pcie_params()
315 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ in qib_pcie_params()
318 dd->lbus_speed = 5000; /* Gen1, 5GHz */ in qib_pcie_params()
321 dd->lbus_speed = 2500; in qib_pcie_params()
330 qib_dev_err(dd, in qib_pcie_params()
334 qib_tune_pcie_caps(dd); in qib_pcie_params()
336 qib_tune_pcie_coalesce(dd); in qib_pcie_params()
340 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in qib_pcie_params()
341 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); in qib_pcie_params()
353 int qib_reinit_intr(struct qib_devdata *dd) in qib_reinit_intr() argument
360 if (!dd->msi_lo) in qib_reinit_intr()
363 pos = dd->pcidev->msi_cap; in qib_reinit_intr()
365 qib_dev_err(dd, in qib_reinit_intr()
371 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, in qib_reinit_intr()
372 dd->msi_lo); in qib_reinit_intr()
373 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, in qib_reinit_intr()
374 dd->msi_hi); in qib_reinit_intr()
375 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); in qib_reinit_intr()
378 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, in qib_reinit_intr()
382 pci_write_config_word(dd->pcidev, pos + in qib_reinit_intr()
384 dd->msi_data); in qib_reinit_intr()
387 if (!ret && (dd->flags & QIB_HAS_INTX)) { in qib_reinit_intr()
388 qib_enable_intx(dd->pcidev); in qib_reinit_intr()
393 pci_set_master(dd->pcidev); in qib_reinit_intr()
403 void qib_nomsi(struct qib_devdata *dd) in qib_nomsi() argument
405 dd->msi_lo = 0; in qib_nomsi()
406 pci_disable_msi(dd->pcidev); in qib_nomsi()
412 void qib_nomsix(struct qib_devdata *dd) in qib_nomsix() argument
414 pci_disable_msix(dd->pcidev); in qib_nomsix()
454 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) in qib_pcie_getcmd() argument
456 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); in qib_pcie_getcmd()
457 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); in qib_pcie_getcmd()
458 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); in qib_pcie_getcmd()
461 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) in qib_pcie_reenable() argument
465 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in qib_pcie_reenable()
466 dd->pcibar0); in qib_pcie_reenable()
468 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r); in qib_pcie_reenable()
469 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in qib_pcie_reenable()
470 dd->pcibar1); in qib_pcie_reenable()
472 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r); in qib_pcie_reenable()
474 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); in qib_pcie_reenable()
475 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); in qib_pcie_reenable()
476 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); in qib_pcie_reenable()
477 r = pci_enable_device(dd->pcidev); in qib_pcie_reenable()
479 qib_dev_err(dd, in qib_pcie_reenable()
494 static void qib_tune_pcie_coalesce(struct qib_devdata *dd) in qib_tune_pcie_coalesce() argument
505 parent = dd->pcidev->bus->self; in qib_tune_pcie_coalesce()
507 qib_devinfo(dd->pcidev, "Parent not root\n"); in qib_tune_pcie_coalesce()
562 static void qib_tune_pcie_caps(struct qib_devdata *dd) in qib_tune_pcie_caps() argument
569 parent = dd->pcidev->bus->self; in qib_tune_pcie_caps()
571 qib_devinfo(dd->pcidev, "Parent not root\n"); in qib_tune_pcie_caps()
575 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) in qib_tune_pcie_caps()
581 ep_mpss = dd->pcidev->pcie_mpss; in qib_tune_pcie_caps()
582 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in qib_tune_pcie_caps()
599 pcie_set_mps(dd->pcidev, 128 << ep_mps); in qib_tune_pcie_caps()
613 ep_mrrs = pcie_get_readrq(dd->pcidev); in qib_tune_pcie_caps()
621 pcie_set_readrq(dd->pcidev, ep_mrrs); in qib_tune_pcie_caps()
633 struct qib_devdata *dd = pci_get_drvdata(pdev); in qib_pci_error_detected() local
649 if (dd) { in qib_pci_error_detected()
651 dd->flags &= ~QIB_PRESENT; in qib_pci_error_detected()
652 qib_disable_after_error(dd); in qib_pci_error_detected()
670 struct qib_devdata *dd = pci_get_drvdata(pdev); in qib_pci_mmio_enabled() local
673 if (dd && dd->pport) { in qib_pci_mmio_enabled()
674 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); in qib_pci_mmio_enabled()
701 struct qib_devdata *dd = pci_get_drvdata(pdev); in qib_pci_resume() local
710 qib_init(dd, 1); /* same as re-init after reset */ in qib_pci_resume()