Lines Matching refs:dd
162 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ argument
164 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ argument
749 static inline void qib_write_kreg(const struct qib_devdata *dd,
758 static void qib_setup_dca(struct qib_devdata *dd);
759 static void setup_dca_notifier(struct qib_devdata *dd,
761 static void reset_dca_notifier(struct qib_devdata *dd,
775 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, in qib_read_ureg32() argument
778 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
781 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg32()
782 (char __iomem *)dd->userbase : in qib_read_ureg32()
783 (char __iomem *)dd->kregbase + dd->uregbase))); in qib_read_ureg32()
796 static inline u64 qib_read_ureg(const struct qib_devdata *dd, in qib_read_ureg() argument
800 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg()
803 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg()
804 (char __iomem *)dd->userbase : in qib_read_ureg()
805 (char __iomem *)dd->kregbase + dd->uregbase))); in qib_read_ureg()
817 static inline void qib_write_ureg(const struct qib_devdata *dd, in qib_write_ureg() argument
822 if (dd->userbase) in qib_write_ureg()
824 ((char __iomem *) dd->userbase + in qib_write_ureg()
825 dd->ureg_align * ctxt); in qib_write_ureg()
828 (dd->uregbase + in qib_write_ureg()
829 (char __iomem *) dd->kregbase + in qib_write_ureg()
830 dd->ureg_align * ctxt); in qib_write_ureg()
832 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_ureg()
836 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, in qib_read_kreg32() argument
839 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg32()
841 return readl((u32 __iomem *) &dd->kregbase[regno]); in qib_read_kreg32()
844 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, in qib_read_kreg64() argument
847 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg64()
849 return readq(&dd->kregbase[regno]); in qib_read_kreg64()
852 static inline void qib_write_kreg(const struct qib_devdata *dd, in qib_write_kreg() argument
855 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_kreg()
856 writeq(value, &dd->kregbase[regno]); in qib_write_kreg()
866 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) in qib_read_kreg_port()
874 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && in qib_write_kreg_port()
875 (ppd->dd->flags & QIB_PRESENT)) in qib_write_kreg_port()
886 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, in qib_write_kreg_ctxt() argument
890 qib_write_kreg(dd, regno + ctxt, value); in qib_write_kreg_ctxt()
893 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) in read_7322_creg() argument
895 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg()
897 return readq(&dd->cspec->cregbase[regno]); in read_7322_creg()
902 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) in read_7322_creg32() argument
904 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg32()
906 return readl(&dd->cspec->cregbase[regno]); in read_7322_creg32()
915 (ppd->dd->flags & QIB_PRESENT)) in write_7322_creg_port()
923 !(ppd->dd->flags & QIB_PRESENT)) in read_7322_creg_port()
932 !(ppd->dd->flags & QIB_PRESENT)) in read_7322_creg32_port()
1349 struct qib_devdata *dd = ppd->dd; in qib_disarm_7322_senderrbufs() local
1352 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in qib_disarm_7322_senderrbufs()
1362 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i); in qib_disarm_7322_senderrbufs()
1365 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]); in qib_disarm_7322_senderrbufs()
1370 qib_disarm_piobufs_set(dd, sbuf, piobcnt); in qib_disarm_7322_senderrbufs()
1427 struct qib_devdata *dd = ppd->dd; in flush_fifo() local
1458 if (dd->flags & QIB_PIO_FLUSH_WC) { in flush_fifo()
1466 qib_sendbuf_done(dd, bufn); in flush_fifo()
1474 struct qib_devdata *dd = ppd->dd; in qib_7322_sdma_sendctrl() local
1502 spin_lock(&dd->sendctrl_lock); in qib_7322_sdma_sendctrl()
1508 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_sdma_sendctrl()
1520 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_sdma_sendctrl()
1525 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_sdma_sendctrl()
1528 spin_unlock(&dd->sendctrl_lock); in qib_7322_sdma_sendctrl()
1530 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) in qib_7322_sdma_sendctrl()
1598 struct qib_devdata *dd = ppd->dd; in sdma_7322_p_errors() local
1605 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, in sdma_7322_p_errors()
1612 qib_dev_porterr(dd, ppd->port, in sdma_7322_p_errors()
1659 static noinline void handle_7322_errors(struct qib_devdata *dd) in handle_7322_errors() argument
1668 errs = qib_read_kreg64(dd, kr_errstatus); in handle_7322_errors()
1670 qib_devinfo(dd->pcidev, in handle_7322_errors()
1676 errs &= dd->cspec->errormask; in handle_7322_errors()
1677 msg = dd->cspec->emsgbuf; in handle_7322_errors()
1682 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_7322_errors()
1685 if (errs & dd->eep_st_masks[log_idx].errs_to_log) in handle_7322_errors()
1686 qib_inc_eeprom_err(dd, log_idx, 1); in handle_7322_errors()
1689 qib_disarm_7322_senderrbufs(dd->pport); in handle_7322_errors()
1695 qib_disarm_7322_senderrbufs(dd->pport); in handle_7322_errors()
1697 qib_write_kreg(dd, kr_errclear, errs); in handle_7322_errors()
1707 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, in handle_7322_errors()
1717 qib_dev_err(dd, in handle_7322_errors()
1719 dd->flags &= ~QIB_INITTED; /* needs re-init */ in handle_7322_errors()
1721 *dd->devstatusp |= QIB_STATUS_HWERROR; in handle_7322_errors()
1722 for (pidx = 0; pidx < dd->num_pports; ++pidx) in handle_7322_errors()
1723 if (dd->pport[pidx].link_speed_supported) in handle_7322_errors()
1724 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; in handle_7322_errors()
1728 qib_dev_err(dd, "%s error\n", msg); in handle_7322_errors()
1738 qib_handle_urcv(dd, ~0U); in handle_7322_errors()
1751 struct qib_devdata *dd = (struct qib_devdata *)data; in qib_error_tasklet() local
1753 handle_7322_errors(dd); in qib_error_tasklet()
1754 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_error_tasklet()
1816 if (!ppd->dd->cspec->r1) in handle_serdes_issues()
1825 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && in handle_serdes_issues()
1837 if (!ppd->dd->cspec->r1 && in handle_serdes_issues()
1852 ppd->dd->cspec->r1 ? in handle_serdes_issues()
1857 ppd->dd->unit, ppd->port, ibclt); in handle_serdes_issues()
1873 struct qib_devdata *dd = ppd->dd; in handle_7322_p_errors() local
1876 fmask = qib_read_kreg64(dd, kr_act_fmask); in handle_7322_p_errors()
1882 qib_devinfo(dd->pcidev, in handle_7322_p_errors()
1899 qib_dev_porterr(dd, ppd->port, in handle_7322_p_errors()
2016 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); in handle_7322_p_errors()
2025 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) in qib_7322_set_intr_state() argument
2028 if (dd->flags & QIB_BADINTR) in qib_7322_set_intr_state()
2030 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); in qib_7322_set_intr_state()
2032 qib_write_kreg(dd, kr_intclear, 0ULL); in qib_7322_set_intr_state()
2033 if (dd->cspec->num_msix_entries) { in qib_7322_set_intr_state()
2035 u64 val = qib_read_kreg64(dd, kr_intgranted); in qib_7322_set_intr_state()
2038 qib_write_kreg(dd, kr_intgranted, val); in qib_7322_set_intr_state()
2041 qib_write_kreg(dd, kr_intmask, 0ULL); in qib_7322_set_intr_state()
2059 static void qib_7322_clear_freeze(struct qib_devdata *dd) in qib_7322_clear_freeze() argument
2064 qib_write_kreg(dd, kr_errmask, 0ULL); in qib_7322_clear_freeze()
2066 for (pidx = 0; pidx < dd->num_pports; ++pidx) in qib_7322_clear_freeze()
2067 if (dd->pport[pidx].link_speed_supported) in qib_7322_clear_freeze()
2068 qib_write_kreg_port(dd->pport + pidx, krp_errmask, in qib_7322_clear_freeze()
2072 qib_7322_set_intr_state(dd, 0); in qib_7322_clear_freeze()
2075 qib_write_kreg(dd, kr_control, dd->control); in qib_7322_clear_freeze()
2076 qib_read_kreg32(dd, kr_scratch); in qib_7322_clear_freeze()
2084 qib_write_kreg(dd, kr_hwerrclear, 0ULL); in qib_7322_clear_freeze()
2085 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); in qib_7322_clear_freeze()
2086 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_7322_clear_freeze()
2088 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in qib_7322_clear_freeze()
2089 if (!dd->pport[pidx].link_speed_supported) in qib_7322_clear_freeze()
2091 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); in qib_7322_clear_freeze()
2092 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); in qib_7322_clear_freeze()
2094 qib_7322_set_intr_state(dd, 1); in qib_7322_clear_freeze()
2109 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, in qib_7322_handle_hwerrors() argument
2116 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); in qib_7322_handle_hwerrors()
2120 qib_dev_err(dd, in qib_7322_handle_hwerrors()
2127 qib_write_kreg(dd, kr_hwerrclear, hwerrs & in qib_7322_handle_hwerrors()
2130 hwerrs &= dd->cspec->hwerrmask; in qib_7322_handle_hwerrors()
2135 qib_devinfo(dd->pcidev, in qib_7322_handle_hwerrors()
2139 ctrl = qib_read_kreg32(dd, kr_control); in qib_7322_handle_hwerrors()
2140 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { in qib_7322_handle_hwerrors()
2145 dd->cspec->stay_in_freeze) { in qib_7322_handle_hwerrors()
2153 if (dd->flags & QIB_INITTED) in qib_7322_handle_hwerrors()
2156 qib_7322_clear_freeze(dd); in qib_7322_handle_hwerrors()
2165 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_7322_handle_hwerrors()
2166 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_handle_hwerrors()
2173 qib_dev_err(dd, "%s hardware error\n", msg); in qib_7322_handle_hwerrors()
2181 struct qib_pportdata *ppd = dd->pport; in qib_7322_handle_hwerrors()
2183 for (; pidx < dd->num_pports; ++pidx, ppd++) { in qib_7322_handle_hwerrors()
2199 if (isfatal && !dd->diag_client) { in qib_7322_handle_hwerrors()
2200 qib_dev_err(dd, in qib_7322_handle_hwerrors()
2202 dd->serial); in qib_7322_handle_hwerrors()
2207 if (dd->freezemsg) in qib_7322_handle_hwerrors()
2208 snprintf(dd->freezemsg, dd->freezelen, in qib_7322_handle_hwerrors()
2210 qib_disable_after_error(dd); in qib_7322_handle_hwerrors()
2225 static void qib_7322_init_hwerrors(struct qib_devdata *dd) in qib_7322_init_hwerrors() argument
2230 extsval = qib_read_kreg64(dd, kr_extstatus); in qib_7322_init_hwerrors()
2233 qib_dev_err(dd, "MemBIST did not complete!\n"); in qib_7322_init_hwerrors()
2236 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); in qib_7322_init_hwerrors()
2237 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_init_hwerrors()
2240 qib_write_kreg(dd, kr_errclear, ~0ULL); in qib_7322_init_hwerrors()
2242 qib_write_kreg(dd, kr_errmask, ~0ULL); in qib_7322_init_hwerrors()
2243 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_7322_init_hwerrors()
2244 for (pidx = 0; pidx < dd->num_pports; ++pidx) in qib_7322_init_hwerrors()
2245 if (dd->pport[pidx].link_speed_supported) in qib_7322_init_hwerrors()
2246 qib_write_kreg_port(dd->pport + pidx, krp_errmask, in qib_7322_init_hwerrors()
2256 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) in qib_set_7322_armlaunch() argument
2259 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH); in qib_set_7322_armlaunch()
2260 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2262 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2263 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_7322_armlaunch()
2275 struct qib_devdata *dd = ppd->dd; in qib_set_ib_7322_lstate() local
2313 qib_write_kreg(dd, kr_scratch, 0); in qib_set_ib_7322_lstate()
2326 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports)) argument
2331 struct qib_devdata *dd = ppd->dd; in set_vls() local
2343 totcred = NUM_RCV_BUF_UNITS(dd); in set_vls()
2359 qib_write_kreg(dd, kr_scratch, 0ULL); in set_vls()
2372 qib_write_kreg(dd, kr_scratch, 0ULL); in set_vls()
2387 struct qib_devdata *dd = ppd->dd; in qib_7322_bringup_serdes() local
2400 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_bringup_serdes()
2492 if (dd->base_guid) in qib_7322_bringup_serdes()
2493 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; in qib_7322_bringup_serdes()
2499 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_bringup_serdes()
2509 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_bringup_serdes()
2514 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2517 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2545 if (ppd->dd->cspec->r1) in qib_7322_mini_quiet_serdes()
2568 struct qib_devdata *dd = ppd->dd; in qib_7322_mini_quiet_serdes() local
2572 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); in qib_7322_mini_quiet_serdes()
2573 qib_write_kreg(dd, kr_hwdiagctrl, in qib_7322_mini_quiet_serdes()
2601 qib_write_kreg(dd, kr_hwdiagctrl, diagc); in qib_7322_mini_quiet_serdes()
2629 struct qib_devdata *dd = ppd->dd; in qib_setup_7322_setextled() local
2638 if (dd->diag_client) in qib_setup_7322_setextled()
2655 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2656 extctl = dd->cspec->extctrl & (ppd->port == 1 ? in qib_setup_7322_setextled()
2670 dd->cspec->extctrl = extctl; in qib_setup_7322_setextled()
2671 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_setup_7322_setextled()
2672 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2680 static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event) in qib_7322_notify_dca() argument
2684 if (dd->flags & QIB_DCA_ENABLED) in qib_7322_notify_dca()
2686 if (!dca_add_requester(&dd->pcidev->dev)) { in qib_7322_notify_dca()
2687 qib_devinfo(dd->pcidev, "DCA enabled\n"); in qib_7322_notify_dca()
2688 dd->flags |= QIB_DCA_ENABLED; in qib_7322_notify_dca()
2689 qib_setup_dca(dd); in qib_7322_notify_dca()
2693 if (dd->flags & QIB_DCA_ENABLED) { in qib_7322_notify_dca()
2694 dca_remove_requester(&dd->pcidev->dev); in qib_7322_notify_dca()
2695 dd->flags &= ~QIB_DCA_ENABLED; in qib_7322_notify_dca()
2696 dd->cspec->dca_ctrl = 0; in qib_7322_notify_dca()
2697 qib_write_kreg(dd, KREG_IDX(DCACtrlA), in qib_7322_notify_dca()
2698 dd->cspec->dca_ctrl); in qib_7322_notify_dca()
2707 struct qib_devdata *dd = rcd->dd; in qib_update_rhdrq_dca() local
2708 struct qib_chip_specific *cspec = dd->cspec; in qib_update_rhdrq_dca()
2710 if (!(dd->flags & QIB_DCA_ENABLED)) in qib_update_rhdrq_dca()
2719 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb; in qib_update_rhdrq_dca()
2720 qib_devinfo(dd->pcidev, in qib_update_rhdrq_dca()
2723 qib_write_kreg(dd, rmp->regno, in qib_update_rhdrq_dca()
2726 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_rhdrq_dca()
2732 struct qib_devdata *dd = ppd->dd; in qib_update_sdma_dca() local
2733 struct qib_chip_specific *cspec = dd->cspec; in qib_update_sdma_dca()
2736 if (!(dd->flags & QIB_DCA_ENABLED)) in qib_update_sdma_dca()
2744 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << in qib_update_sdma_dca()
2748 qib_devinfo(dd->pcidev, in qib_update_sdma_dca()
2751 qib_write_kreg(dd, KREG_IDX(DCACtrlF), in qib_update_sdma_dca()
2756 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_sdma_dca()
2760 static void qib_setup_dca(struct qib_devdata *dd) in qib_setup_dca() argument
2762 struct qib_chip_specific *cspec = dd->cspec; in qib_setup_dca()
2793 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i, in qib_setup_dca()
2796 setup_dca_notifier(dd, &cspec->msix_entries[i]); in qib_setup_dca()
2821 struct qib_devdata *dd; in qib_irq_notifier_release() local
2826 dd = rcd->dd; in qib_irq_notifier_release()
2830 dd = ppd->dd; in qib_irq_notifier_release()
2832 qib_devinfo(dd->pcidev, in qib_irq_notifier_release()
2843 static void qib_7322_nomsix(struct qib_devdata *dd) in qib_7322_nomsix() argument
2848 dd->cspec->main_int_mask = ~0ULL; in qib_7322_nomsix()
2849 n = dd->cspec->num_msix_entries; in qib_7322_nomsix()
2853 dd->cspec->num_msix_entries = 0; in qib_7322_nomsix()
2856 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]); in qib_7322_nomsix()
2859 dd->cspec->msix_entries[i].msix.vector, NULL); in qib_7322_nomsix()
2860 free_cpumask_var(dd->cspec->msix_entries[i].mask); in qib_7322_nomsix()
2861 free_irq(dd->cspec->msix_entries[i].msix.vector, in qib_7322_nomsix()
2862 dd->cspec->msix_entries[i].arg); in qib_7322_nomsix()
2864 qib_nomsix(dd); in qib_7322_nomsix()
2867 intgranted = qib_read_kreg64(dd, kr_intgranted); in qib_7322_nomsix()
2869 qib_write_kreg(dd, kr_intgranted, intgranted); in qib_7322_nomsix()
2872 static void qib_7322_free_irq(struct qib_devdata *dd) in qib_7322_free_irq() argument
2874 if (dd->cspec->irq) { in qib_7322_free_irq()
2875 free_irq(dd->cspec->irq, dd); in qib_7322_free_irq()
2876 dd->cspec->irq = 0; in qib_7322_free_irq()
2878 qib_7322_nomsix(dd); in qib_7322_free_irq()
2881 static void qib_setup_7322_cleanup(struct qib_devdata *dd) in qib_setup_7322_cleanup() argument
2886 if (dd->flags & QIB_DCA_ENABLED) { in qib_setup_7322_cleanup()
2887 dca_remove_requester(&dd->pcidev->dev); in qib_setup_7322_cleanup()
2888 dd->flags &= ~QIB_DCA_ENABLED; in qib_setup_7322_cleanup()
2889 dd->cspec->dca_ctrl = 0; in qib_setup_7322_cleanup()
2890 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); in qib_setup_7322_cleanup()
2894 qib_7322_free_irq(dd); in qib_setup_7322_cleanup()
2895 kfree(dd->cspec->cntrs); in qib_setup_7322_cleanup()
2896 kfree(dd->cspec->sendchkenable); in qib_setup_7322_cleanup()
2897 kfree(dd->cspec->sendgrhchk); in qib_setup_7322_cleanup()
2898 kfree(dd->cspec->sendibchk); in qib_setup_7322_cleanup()
2899 kfree(dd->cspec->msix_entries); in qib_setup_7322_cleanup()
2900 for (i = 0; i < dd->num_pports; i++) { in qib_setup_7322_cleanup()
2905 kfree(dd->pport[i].cpspec->portcntrs); in qib_setup_7322_cleanup()
2906 if (dd->flags & QIB_HAS_QSFP) { in qib_setup_7322_cleanup()
2907 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2908 dd->cspec->gpio_mask &= ~mask; in qib_setup_7322_cleanup()
2909 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_7322_cleanup()
2910 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2911 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data); in qib_setup_7322_cleanup()
2913 if (dd->pport[i].ibport_data.smi_ah) in qib_setup_7322_cleanup()
2914 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah); in qib_setup_7322_cleanup()
2919 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) in sdma_7322_intr() argument
2921 struct qib_pportdata *ppd0 = &dd->pport[0]; in sdma_7322_intr()
2922 struct qib_pportdata *ppd1 = &dd->pport[1]; in sdma_7322_intr()
2942 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) in qib_wantpiobuf_7322_intr() argument
2946 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_wantpiobuf_7322_intr()
2948 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2950 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2951 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in qib_wantpiobuf_7322_intr()
2952 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_wantpiobuf_7322_intr()
2953 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_wantpiobuf_7322_intr()
2961 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) in unknown_7322_ibits() argument
2967 qib_dev_err(dd, in unknown_7322_ibits()
2970 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); in unknown_7322_ibits()
2974 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) in unknown_7322_gpio_intr() argument
2987 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); in unknown_7322_gpio_intr()
2995 qib_write_kreg(dd, kr_gpio_clear, gpiostatus); in unknown_7322_gpio_intr()
3000 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); in unknown_7322_gpio_intr()
3006 if (!dd->pport[pidx].link_speed_supported) in unknown_7322_gpio_intr()
3009 ppd = dd->pport + pidx; in unknown_7322_gpio_intr()
3011 if (gpiostatus & dd->cspec->gpio_mask & mask) { in unknown_7322_gpio_intr()
3016 pins = qib_read_kreg64(dd, kr_extstatus); in unknown_7322_gpio_intr()
3027 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); in unknown_7322_gpio_intr()
3033 dd->cspec->gpio_mask &= ~gpio_irq; in unknown_7322_gpio_intr()
3034 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in unknown_7322_gpio_intr()
3042 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) in unlikely_7322_intr() argument
3045 unknown_7322_ibits(dd, istat); in unlikely_7322_intr()
3047 unknown_7322_gpio_intr(dd); in unlikely_7322_intr()
3049 qib_write_kreg(dd, kr_errmask, 0ULL); in unlikely_7322_intr()
3050 tasklet_schedule(&dd->error_tasklet); in unlikely_7322_intr()
3052 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) in unlikely_7322_intr()
3053 handle_7322_p_errors(dd->rcd[0]->ppd); in unlikely_7322_intr()
3054 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) in unlikely_7322_intr()
3055 handle_7322_p_errors(dd->rcd[1]->ppd); in unlikely_7322_intr()
3064 struct qib_devdata *dd = rcd->dd; in adjust_rcv_timeout() local
3065 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
3078 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
3079 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); in adjust_rcv_timeout()
3092 struct qib_devdata *dd = data; in qib_7322intr() local
3100 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { in qib_7322intr()
3111 istat = qib_read_kreg64(dd, kr_intstatus); in qib_7322intr()
3114 qib_bad_intrstatus(dd); in qib_7322intr()
3115 qib_dev_err(dd, "Interrupt status all f's, skipping\n"); in qib_7322intr()
3121 istat &= dd->cspec->main_int_mask; in qib_7322intr()
3128 this_cpu_inc(*dd->int_counter); in qib_7322intr()
3134 unlikely_7322_intr(dd, istat); in qib_7322intr()
3142 qib_write_kreg(dd, kr_intclear, istat); in qib_7322intr()
3153 for (i = 0; i < dd->first_user_ctxt; i++) { in qib_7322intr()
3156 if (dd->rcd[i]) in qib_7322intr()
3157 qib_kreceive(dd->rcd[i], NULL, &npkts); in qib_7322intr()
3164 qib_handle_urcv(dd, ctxtrbits); in qib_7322intr()
3169 sdma_7322_intr(dd, istat); in qib_7322intr()
3171 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) in qib_7322intr()
3172 qib_ib_piobufavail(dd); in qib_7322intr()
3185 struct qib_devdata *dd = rcd->dd; in qib_7322pintr() local
3188 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in qib_7322pintr()
3197 this_cpu_inc(*dd->int_counter); in qib_7322pintr()
3200 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | in qib_7322pintr()
3213 struct qib_devdata *dd = data; in qib_7322bufavail() local
3215 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in qib_7322bufavail()
3224 this_cpu_inc(*dd->int_counter); in qib_7322bufavail()
3227 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL); in qib_7322bufavail()
3230 if (dd->flags & QIB_INITTED) in qib_7322bufavail()
3231 qib_ib_piobufavail(dd); in qib_7322bufavail()
3233 qib_wantpiobuf_7322_intr(dd, 0); in qib_7322bufavail()
3244 struct qib_devdata *dd = ppd->dd; in sdma_intr() local
3246 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_intr()
3255 this_cpu_inc(*dd->int_counter); in sdma_intr()
3258 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_intr()
3271 struct qib_devdata *dd = ppd->dd; in sdma_idle_intr() local
3273 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_idle_intr()
3282 this_cpu_inc(*dd->int_counter); in sdma_idle_intr()
3285 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_idle_intr()
3298 struct qib_devdata *dd = ppd->dd; in sdma_progress_intr() local
3300 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_progress_intr()
3309 this_cpu_inc(*dd->int_counter); in sdma_progress_intr()
3312 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_progress_intr()
3326 struct qib_devdata *dd = ppd->dd; in sdma_cleanup_intr() local
3328 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_cleanup_intr()
3337 this_cpu_inc(*dd->int_counter); in sdma_cleanup_intr()
3340 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_cleanup_intr()
3350 static void reset_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m) in reset_dca_notifier() argument
3354 qib_devinfo(dd->pcidev, in reset_dca_notifier()
3356 dd->unit, in reset_dca_notifier()
3364 static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m) in setup_dca_notifier() argument
3380 qib_devinfo(dd->pcidev, in setup_dca_notifier()
3403 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) in qib_setup_7322_interrupt() argument
3411 if (!dd->num_pports) in qib_setup_7322_interrupt()
3420 qib_7322_set_intr_state(dd, 0); in qib_setup_7322_interrupt()
3423 qib_7322_init_hwerrors(dd); in qib_setup_7322_interrupt()
3426 qib_write_kreg(dd, kr_intclear, ~0ULL); in qib_setup_7322_interrupt()
3429 qib_write_kreg(dd, kr_intgranted, ~0ULL); in qib_setup_7322_interrupt()
3430 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL); in qib_setup_7322_interrupt()
3433 if (!dd->cspec->num_msix_entries) { in qib_setup_7322_interrupt()
3436 if (!dd->pcidev->irq) { in qib_setup_7322_interrupt()
3437 qib_dev_err(dd, in qib_setup_7322_interrupt()
3441 ret = request_irq(dd->pcidev->irq, qib_7322intr, in qib_setup_7322_interrupt()
3442 IRQF_SHARED, QIB_DRV_NAME, dd); in qib_setup_7322_interrupt()
3444 qib_dev_err(dd, in qib_setup_7322_interrupt()
3446 dd->pcidev->irq, ret); in qib_setup_7322_interrupt()
3449 dd->cspec->irq = dd->pcidev->irq; in qib_setup_7322_interrupt()
3450 dd->cspec->main_int_mask = ~0ULL; in qib_setup_7322_interrupt()
3458 local_mask = cpumask_of_pcibus(dd->pcidev->bus); in qib_setup_7322_interrupt()
3471 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { in qib_setup_7322_interrupt()
3480 dd->cspec->msix_entries[msixnum]. in qib_setup_7322_interrupt()
3481 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1] in qib_setup_7322_interrupt()
3486 if (irq_table[i].port > dd->num_pports) in qib_setup_7322_interrupt()
3488 arg = dd->pport + irq_table[i].port - 1; in qib_setup_7322_interrupt()
3490 arg = dd; in qib_setup_7322_interrupt()
3496 snprintf(dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3497 sizeof(dd->cspec->msix_entries[msixnum].name) in qib_setup_7322_interrupt()
3499 QIB_DRV_NAME "%d%s", dd->unit, in qib_setup_7322_interrupt()
3506 arg = dd->rcd[ctxt]; in qib_setup_7322_interrupt()
3516 snprintf(dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3517 sizeof(dd->cspec->msix_entries[msixnum].name) in qib_setup_7322_interrupt()
3519 QIB_DRV_NAME "%d (kctx)", dd->unit); in qib_setup_7322_interrupt()
3522 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3523 handler, 0, dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3530 qib_dev_err(dd, in qib_setup_7322_interrupt()
3533 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3535 qib_7322_nomsix(dd); in qib_setup_7322_interrupt()
3538 dd->cspec->msix_entries[msixnum].arg = arg; in qib_setup_7322_interrupt()
3540 dd->cspec->msix_entries[msixnum].dca = dca; in qib_setup_7322_interrupt()
3541 dd->cspec->msix_entries[msixnum].rcv = in qib_setup_7322_interrupt()
3551 val = qib_read_kreg64(dd, 2 * msixnum + 1 + in qib_setup_7322_interrupt()
3555 &dd->cspec->msix_entries[msixnum].mask, in qib_setup_7322_interrupt()
3559 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3566 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3569 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3570 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3576 qib_write_kreg(dd, kr_intredirect + i, redirect[i]); in qib_setup_7322_interrupt()
3577 dd->cspec->main_int_mask = mask; in qib_setup_7322_interrupt()
3578 tasklet_init(&dd->error_tasklet, qib_error_tasklet, in qib_setup_7322_interrupt()
3579 (unsigned long)dd); in qib_setup_7322_interrupt()
3589 static unsigned qib_7322_boardname(struct qib_devdata *dd) in qib_7322_boardname() argument
3596 boardid = SYM_FIELD(dd->revision, Revision, BoardID); in qib_7322_boardname()
3604 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3609 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3616 qib_dev_err(dd, "Unsupported version of QMH7342\n"); in qib_7322_boardname()
3628 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3632 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3636 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3640 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid); in qib_7322_boardname()
3643 dd->board_atten = 1; /* index into txdds_Xdr */ in qib_7322_boardname()
3646 dd->boardname = kmalloc(namelen, GFP_KERNEL); in qib_7322_boardname()
3647 if (!dd->boardname) in qib_7322_boardname()
3648 qib_dev_err(dd, "Failed allocation for board name: %s\n", n); in qib_7322_boardname()
3650 snprintf(dd->boardname, namelen, "%s", n); in qib_7322_boardname()
3652 snprintf(dd->boardversion, sizeof(dd->boardversion), in qib_7322_boardname()
3654 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, in qib_7322_boardname()
3655 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch), in qib_7322_boardname()
3656 dd->majrev, dd->minrev, in qib_7322_boardname()
3657 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW)); in qib_7322_boardname()
3660 qib_devinfo(dd->pcidev, in qib_7322_boardname()
3662 dd->unit); in qib_7322_boardname()
3673 static int qib_do_7322_reset(struct qib_devdata *dd) in qib_do_7322_reset() argument
3683 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); in qib_do_7322_reset()
3685 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); in qib_do_7322_reset()
3687 msix_entries = dd->cspec->num_msix_entries; in qib_do_7322_reset()
3690 qib_7322_set_intr_state(dd, 0); in qib_do_7322_reset()
3693 qib_7322_nomsix(dd); in qib_do_7322_reset()
3695 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * in qib_do_7322_reset()
3698 qib_dev_err(dd, "No mem to save MSIx data\n"); in qib_do_7322_reset()
3712 vecaddr = qib_read_kreg64(dd, 2 * i + in qib_do_7322_reset()
3714 vecdata = qib_read_kreg64(dd, 1 + 2 * i + in qib_do_7322_reset()
3723 dd->pport->cpspec->ibdeltainprog = 0; in qib_do_7322_reset()
3724 dd->pport->cpspec->ibsymdelta = 0; in qib_do_7322_reset()
3725 dd->pport->cpspec->iblnkerrdelta = 0; in qib_do_7322_reset()
3726 dd->pport->cpspec->ibmalfdelta = 0; in qib_do_7322_reset()
3728 dd->z_int_counter = qib_int_counter(dd); in qib_do_7322_reset()
3735 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); in qib_do_7322_reset()
3736 dd->flags |= QIB_DOING_RESET; in qib_do_7322_reset()
3737 val = dd->control | QLOGIC_IB_C_RESET; in qib_do_7322_reset()
3738 writeq(val, &dd->kregbase[kr_control]); in qib_do_7322_reset()
3748 qib_pcie_reenable(dd, cmdval, int_line, clinesz); in qib_do_7322_reset()
3754 val = readq(&dd->kregbase[kr_revision]); in qib_do_7322_reset()
3755 if (val == dd->revision) in qib_do_7322_reset()
3758 qib_dev_err(dd, in qib_do_7322_reset()
3765 dd->flags |= QIB_PRESENT; /* it's back */ in qib_do_7322_reset()
3770 dd->cspec->msix_entries[i].msix.entry = i; in qib_do_7322_reset()
3773 qib_write_kreg(dd, 2 * i + in qib_do_7322_reset()
3776 qib_write_kreg(dd, 1 + 2 * i + in qib_do_7322_reset()
3783 for (i = 0; i < dd->num_pports; ++i) in qib_do_7322_reset()
3784 write_7322_init_portregs(&dd->pport[i]); in qib_do_7322_reset()
3785 write_7322_initregs(dd); in qib_do_7322_reset()
3787 if (qib_pcie_params(dd, dd->lbus_width, in qib_do_7322_reset()
3788 &dd->cspec->num_msix_entries, in qib_do_7322_reset()
3789 dd->cspec->msix_entries)) in qib_do_7322_reset()
3790 qib_dev_err(dd, in qib_do_7322_reset()
3793 qib_setup_7322_interrupt(dd, 1); in qib_do_7322_reset()
3795 for (i = 0; i < dd->num_pports; ++i) { in qib_do_7322_reset()
3796 struct qib_pportdata *ppd = &dd->pport[i]; in qib_do_7322_reset()
3805 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ in qib_do_7322_reset()
3817 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, in qib_7322_put_tid() argument
3820 if (!(dd->flags & QIB_PRESENT)) in qib_7322_put_tid()
3822 if (pa != dd->tidinvalid) { in qib_7322_put_tid()
3827 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", in qib_7322_put_tid()
3832 qib_dev_err(dd, in qib_7322_put_tid()
3839 chippa |= dd->tidtemplate; in qib_7322_put_tid()
3856 static void qib_7322_clear_tids(struct qib_devdata *dd, in qib_7322_clear_tids() argument
3864 if (!dd->kregbase || !rcd) in qib_7322_clear_tids()
3869 tidinv = dd->tidinvalid; in qib_7322_clear_tids()
3871 ((char __iomem *) dd->kregbase + in qib_7322_clear_tids()
3872 dd->rcvtidbase + in qib_7322_clear_tids()
3873 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); in qib_7322_clear_tids()
3875 for (i = 0; i < dd->rcvtidcnt; i++) in qib_7322_clear_tids()
3876 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, in qib_7322_clear_tids()
3880 ((char __iomem *) dd->kregbase + in qib_7322_clear_tids()
3881 dd->rcvegrbase + in qib_7322_clear_tids()
3885 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, in qib_7322_clear_tids()
3895 static void qib_7322_tidtemplate(struct qib_devdata *dd) in qib_7322_tidtemplate() argument
3906 if (dd->rcvegrbufsize == 2048) in qib_7322_tidtemplate()
3907 dd->tidtemplate = IBA7322_TID_SZ_2K; in qib_7322_tidtemplate()
3908 else if (dd->rcvegrbufsize == 4096) in qib_7322_tidtemplate()
3909 dd->tidtemplate = IBA7322_TID_SZ_4K; in qib_7322_tidtemplate()
3910 dd->tidinvalid = 0; in qib_7322_tidtemplate()
3928 if (rcd->dd->cspec->r1) in qib_7322_get_base_info()
3930 if (rcd->dd->flags & QIB_USE_SPCL_TRIG) in qib_7322_get_base_info()
3937 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) in qib_7322_get_msgheader() argument
3942 (rhf_addr - dd->rhf_offset + offset); in qib_7322_get_msgheader()
3948 static void qib_7322_config_ctxts(struct qib_devdata *dd) in qib_7322_config_ctxts() argument
3953 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); in qib_7322_config_ctxts()
3954 dd->cspec->numctxts = nchipctxts; in qib_7322_config_ctxts()
3955 if (qib_n_krcv_queues > 1 && dd->num_pports) { in qib_7322_config_ctxts()
3956 dd->first_user_ctxt = NUM_IB_PORTS + in qib_7322_config_ctxts()
3957 (qib_n_krcv_queues - 1) * dd->num_pports; in qib_7322_config_ctxts()
3958 if (dd->first_user_ctxt > nchipctxts) in qib_7322_config_ctxts()
3959 dd->first_user_ctxt = nchipctxts; in qib_7322_config_ctxts()
3960 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; in qib_7322_config_ctxts()
3962 dd->first_user_ctxt = NUM_IB_PORTS; in qib_7322_config_ctxts()
3963 dd->n_krcv_queues = 1; in qib_7322_config_ctxts()
3967 int nctxts = dd->first_user_ctxt + num_online_cpus(); in qib_7322_config_ctxts()
3970 dd->ctxtcnt = 6; in qib_7322_config_ctxts()
3972 dd->ctxtcnt = 10; in qib_7322_config_ctxts()
3974 dd->ctxtcnt = nchipctxts; in qib_7322_config_ctxts()
3975 } else if (qib_cfgctxts < dd->num_pports) in qib_7322_config_ctxts()
3976 dd->ctxtcnt = dd->num_pports; in qib_7322_config_ctxts()
3978 dd->ctxtcnt = qib_cfgctxts; in qib_7322_config_ctxts()
3979 if (!dd->ctxtcnt) /* none of the above, set to max */ in qib_7322_config_ctxts()
3980 dd->ctxtcnt = nchipctxts; in qib_7322_config_ctxts()
3987 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3988 if (dd->ctxtcnt > 10) in qib_7322_config_ctxts()
3989 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3990 else if (dd->ctxtcnt > 6) in qib_7322_config_ctxts()
3991 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3995 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); in qib_7322_config_ctxts()
4001 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in qib_7322_config_ctxts()
4002 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
4005 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in qib_7322_config_ctxts()
4007 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); in qib_7322_config_ctxts()
4009 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, in qib_7322_config_ctxts()
4010 dd->num_pports > 1 ? 1024U : 2048U); in qib_7322_config_ctxts()
4118 struct qib_devdata *dd = ppd->dd; in qib_7322_set_ib_cfg() local
4203 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
4217 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
4237 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
4254 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
4293 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); in qib_7322_set_ib_cfg()
4324 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", in qib_7322_set_ib_cfg()
4353 if (ppd->dd->cspec->r1) { in qib_7322_set_ib_cfg()
4366 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_set_ib_cfg()
4381 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", in qib_7322_set_loopback()
4382 ppd->dd->unit, ppd->port); in qib_7322_set_loopback()
4388 qib_devinfo(ppd->dd->pcidev, in qib_7322_set_loopback()
4390 ppd->dd->unit, ppd->port); in qib_7322_set_loopback()
4401 qib_write_kreg(ppd->dd, kr_scratch, 0); in qib_7322_set_loopback()
4436 struct qib_devdata *dd = ppd->dd; in set_vl_weights() local
4439 spin_lock_irqsave(&dd->sendctrl_lock, flags); in set_vl_weights()
4442 qib_write_kreg(dd, kr_scratch, 0); in set_vl_weights()
4443 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in set_vl_weights()
4491 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); in qib_update_7322_usrhead()
4493 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4494 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4502 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); in qib_7322_hdrqempty()
4506 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); in qib_7322_hdrqempty()
4536 struct qib_devdata *dd = ppd->dd; in rcvctrl_7322_mod() local
4541 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4544 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4546 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4548 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4550 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4556 mask = (1ULL << dd->ctxtcnt) - 1; in rcvctrl_7322_mod()
4560 rcd = dd->rcd[ctxt]; in rcvctrl_7322_mod()
4565 if (!(dd->flags & QIB_NODMA_RTAIL)) { in rcvctrl_7322_mod()
4567 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4570 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, in rcvctrl_7322_mod()
4572 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, in rcvctrl_7322_mod()
4580 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); in rcvctrl_7322_mod()
4582 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); in rcvctrl_7322_mod()
4584 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4586 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4593 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in rcvctrl_7322_mod()
4596 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { in rcvctrl_7322_mod()
4603 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); in rcvctrl_7322_mod()
4604 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); in rcvctrl_7322_mod()
4607 (void) qib_read_kreg32(dd, kr_scratch); in rcvctrl_7322_mod()
4608 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); in rcvctrl_7322_mod()
4609 dd->rcd[ctxt]->head = val; in rcvctrl_7322_mod()
4611 if (ctxt < dd->first_user_ctxt) in rcvctrl_7322_mod()
4612 val |= dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4613 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_7322_mod()
4615 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { in rcvctrl_7322_mod()
4617 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4618 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_7322_mod()
4625 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); in rcvctrl_7322_mod()
4626 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); in rcvctrl_7322_mod()
4628 qib_write_ureg(dd, ur_rcvflowtable + f, in rcvctrl_7322_mod()
4633 for (i = 0; i < dd->cfgctxts; i++) { in rcvctrl_7322_mod()
4634 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, in rcvctrl_7322_mod()
4636 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0); in rcvctrl_7322_mod()
4638 qib_write_ureg(dd, ur_rcvflowtable + f, in rcvctrl_7322_mod()
4643 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4675 struct qib_devdata *dd = ppd->dd; in sendctrl_7322_mod() local
4679 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_7322_mod()
4683 dd->sendctrl = 0; in sendctrl_7322_mod()
4685 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4687 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4688 if (dd->flags & QIB_USE_SPCL_TRIG) in sendctrl_7322_mod()
4689 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); in sendctrl_7322_mod()
4701 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_7322_mod()
4702 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in sendctrl_7322_mod()
4709 qib_write_kreg(dd, kr_sendctrl, in sendctrl_7322_mod()
4712 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4728 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4731 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_7322_mod()
4738 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) in sendctrl_7322_mod()
4742 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); in sendctrl_7322_mod()
4743 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4748 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4752 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in sendctrl_7322_mod()
4753 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4756 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_7322_mod()
4766 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_7322_mod()
4767 qib_write_kreg(dd, kr_scratch, v); in sendctrl_7322_mod()
4768 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_7322_mod()
4769 qib_write_kreg(dd, kr_scratch, v); in sendctrl_7322_mod()
4770 qib_read_kreg32(dd, kr_scratch); in sendctrl_7322_mod()
4785 struct qib_devdata *dd = ppd->dd; in qib_portcntr_7322() local
4833 qib_devinfo(ppd->dd->pcidev, in qib_portcntr_7322()
4844 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { in qib_portcntr_7322()
4845 struct qib_ctxtdata *rcd = dd->rcd[i]; in qib_portcntr_7322()
4849 ret += read_7322_creg32(dd, cr_base_egrovfl + i); in qib_portcntr_7322()
5041 static void init_7322_cntrnames(struct qib_devdata *dd) in init_7322_cntrnames() argument
5046 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; in init_7322_cntrnames()
5055 dd->cspec->ncntrs = i; in init_7322_cntrnames()
5058 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; in init_7322_cntrnames()
5060 dd->cspec->cntrnamelen = 1 + s - cntr7322names; in init_7322_cntrnames()
5061 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs in init_7322_cntrnames()
5063 if (!dd->cspec->cntrs) in init_7322_cntrnames()
5064 qib_dev_err(dd, "Failed allocation for counters\n"); in init_7322_cntrnames()
5068 dd->cspec->nportcntrs = i - 1; in init_7322_cntrnames()
5069 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; in init_7322_cntrnames()
5070 for (i = 0; i < dd->num_pports; ++i) { in init_7322_cntrnames()
5071 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs in init_7322_cntrnames()
5073 if (!dd->pport[i].cpspec->portcntrs) in init_7322_cntrnames()
5074 qib_dev_err(dd, in init_7322_cntrnames()
5079 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, in qib_read_7322cntrs() argument
5085 ret = dd->cspec->cntrnamelen; in qib_read_7322cntrs()
5091 u64 *cntr = dd->cspec->cntrs; in qib_read_7322cntrs()
5094 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_7322cntrs()
5101 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_7322cntrs()
5103 *cntr++ = read_7322_creg(dd, in qib_read_7322cntrs()
5107 *cntr++ = read_7322_creg32(dd, in qib_read_7322cntrs()
5114 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, in qib_read_7322portcntrs() argument
5120 ret = dd->cspec->portcntrnamelen; in qib_read_7322portcntrs()
5126 struct qib_pportdata *ppd = &dd->pport[port]; in qib_read_7322portcntrs()
5130 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_7322portcntrs()
5137 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_7322portcntrs()
5168 struct qib_devdata *dd = (struct qib_devdata *) opaque; in qib_get_7322_faststats() local
5174 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in qib_get_7322_faststats()
5175 ppd = dd->pport + pidx; in qib_get_7322_faststats()
5182 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) in qib_get_7322_faststats()
5183 || dd->diag_client) in qib_get_7322_faststats()
5193 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); in qib_get_7322_faststats()
5194 traffic_wds -= ppd->dd->traffic_wds; in qib_get_7322_faststats()
5195 ppd->dd->traffic_wds += traffic_wds; in qib_get_7322_faststats()
5196 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); in qib_get_7322_faststats()
5206 ppd->dd->cspec->r1 ? in qib_get_7322_faststats()
5212 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); in qib_get_7322_faststats()
5218 static int qib_7322_intr_fallback(struct qib_devdata *dd) in qib_7322_intr_fallback() argument
5220 if (!dd->cspec->num_msix_entries) in qib_7322_intr_fallback()
5223 qib_devinfo(dd->pcidev, in qib_7322_intr_fallback()
5225 qib_7322_nomsix(dd); in qib_7322_intr_fallback()
5226 qib_enable_intx(dd->pcidev); in qib_7322_intr_fallback()
5227 qib_setup_7322_interrupt(dd, 0); in qib_7322_intr_fallback()
5243 struct qib_devdata *dd = ppd->dd; in qib_7322_mini_pcs_reset() local
5249 qib_write_kreg(dd, kr_hwerrmask, in qib_7322_mini_pcs_reset()
5250 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); in qib_7322_mini_pcs_reset()
5256 qib_read_kreg32(dd, kr_scratch); in qib_7322_mini_pcs_reset()
5259 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_mini_pcs_reset()
5260 qib_write_kreg(dd, kr_hwerrclear, in qib_7322_mini_pcs_reset()
5262 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_mini_pcs_reset()
5280 struct qib_devdata *dd = ppd->dd; in autoneg_7322_sendpkt() local
5292 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); in autoneg_7322_sendpkt()
5297 if (dd->flags & QIB_USE_SPCL_TRIG) { in autoneg_7322_sendpkt()
5298 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; in autoneg_7322_sendpkt()
5304 qib_sendbuf_done(dd, pnum); in autoneg_7322_sendpkt()
5306 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); in autoneg_7322_sendpkt()
5314 struct qib_devdata *dd = ppd->dd; in qib_autoneg_7322_send() local
5349 qib_read_kreg64(dd, kr_scratch); in qib_autoneg_7322_send()
5352 qib_read_kreg64(dd, kr_scratch); in qib_autoneg_7322_send()
5393 qib_write_kreg(ppd->dd, kr_scratch, 0); in set_7322_ibspeed_fast()
5424 struct qib_devdata *dd; in autoneg_7322_work() local
5431 dd = ppd->dd; in autoneg_7322_work()
5644 if (ppd->dd->flags & QIB_HAS_QSFP) { in qib_7322_ib_updown()
5712 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) in qib_7322_ib_updown()
5755 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) in gpio_7322_mod() argument
5764 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5765 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5766 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5767 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_7322_mod()
5769 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_7322_mod()
5770 qib_write_kreg(dd, kr_gpio_out, new_out); in gpio_7322_mod()
5771 dd->cspec->gpio_out = new_out; in gpio_7322_mod()
5772 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5782 read_val = qib_read_kreg64(dd, kr_extstatus); in gpio_7322_mod()
5787 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) in qib_7322_eeprom_wen() argument
5793 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM; in qib_7322_eeprom_wen()
5794 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); in qib_7322_eeprom_wen()
5804 static void get_7322_chip_params(struct qib_devdata *dd) in get_7322_chip_params() argument
5810 dd->palign = qib_read_kreg32(dd, kr_pagealign); in get_7322_chip_params()
5812 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); in get_7322_chip_params()
5814 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); in get_7322_chip_params()
5815 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); in get_7322_chip_params()
5816 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); in get_7322_chip_params()
5817 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); in get_7322_chip_params()
5818 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; in get_7322_chip_params()
5820 val = qib_read_kreg64(dd, kr_sendpiobufcnt); in get_7322_chip_params()
5821 dd->piobcnt2k = val & ~0U; in get_7322_chip_params()
5822 dd->piobcnt4k = val >> 32; in get_7322_chip_params()
5823 val = qib_read_kreg64(dd, kr_sendpiosize); in get_7322_chip_params()
5824 dd->piosize2k = val & ~0U; in get_7322_chip_params()
5825 dd->piosize4k = val >> 32; in get_7322_chip_params()
5830 dd->pport[0].ibmtu = (u32)mtu; in get_7322_chip_params()
5831 dd->pport[1].ibmtu = (u32)mtu; in get_7322_chip_params()
5834 dd->pio2kbase = (u32 __iomem *) in get_7322_chip_params()
5835 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); in get_7322_chip_params()
5836 dd->pio4kbase = (u32 __iomem *) in get_7322_chip_params()
5837 ((char __iomem *) dd->kregbase + in get_7322_chip_params()
5838 (dd->piobufbase >> 32)); in get_7322_chip_params()
5844 dd->align4k = ALIGN(dd->piosize4k, dd->palign); in get_7322_chip_params()
5846 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; in get_7322_chip_params()
5848 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / in get_7322_chip_params()
5857 static void qib_7322_set_baseaddrs(struct qib_devdata *dd) in qib_7322_set_baseaddrs() argument
5861 cregbase = qib_read_kreg32(dd, kr_counterregbase); in qib_7322_set_baseaddrs()
5863 dd->cspec->cregbase = (u64 __iomem *)(cregbase + in qib_7322_set_baseaddrs()
5864 (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5866 dd->egrtidbase = (u64 __iomem *) in qib_7322_set_baseaddrs()
5867 ((char __iomem *) dd->kregbase + dd->rcvegrbase); in qib_7322_set_baseaddrs()
5870 dd->pport[0].cpspec->kpregbase = in qib_7322_set_baseaddrs()
5871 (u64 __iomem *)((char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5872 dd->pport[1].cpspec->kpregbase = in qib_7322_set_baseaddrs()
5873 (u64 __iomem *)(dd->palign + in qib_7322_set_baseaddrs()
5874 (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5875 dd->pport[0].cpspec->cpregbase = in qib_7322_set_baseaddrs()
5876 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], in qib_7322_set_baseaddrs()
5877 kr_counterregbase) + (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5878 dd->pport[1].cpspec->cpregbase = in qib_7322_set_baseaddrs()
5879 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], in qib_7322_set_baseaddrs()
5880 kr_counterregbase) + (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5896 static int sendctrl_hook(struct qib_devdata *dd, in sendctrl_hook() argument
5912 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in sendctrl_hook()
5916 ppd = dd->pport + pidx; in sendctrl_hook()
5921 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); in sendctrl_hook()
5927 if (pidx >= dd->num_pports) in sendctrl_hook()
5937 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_hook()
5947 local_data = (u64)qib_read_kreg32(dd, idx); in sendctrl_hook()
5949 local_data = qib_read_kreg64(dd, idx); in sendctrl_hook()
5970 qib_write_kreg(dd, idx, tval); in sendctrl_hook()
5971 qib_write_kreg(dd, kr_scratch, 0Ull); in sendctrl_hook()
5973 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_hook()
6039 if (!ret && !ppd->dd->cspec->r1) { in qsfp_7322_event()
6081 struct qib_devdata *dd = ppd->dd; in qib_init_7322_qsfp() local
6087 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6088 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6089 dd->cspec->gpio_mask |= mod_prs_bit; in qib_init_7322_qsfp()
6090 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_init_7322_qsfp()
6091 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_init_7322_qsfp()
6092 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6108 static void set_no_qsfp_atten(struct qib_devdata *dd, int change) in set_no_qsfp_atten() argument
6120 for (pidx = 0; pidx < dd->num_pports; ++pidx) in set_no_qsfp_atten()
6121 dd->pport[pidx].cpspec->no_eep = deflt; in set_no_qsfp_atten()
6124 if (IS_QME(dd) || IS_QMH(dd)) in set_no_qsfp_atten()
6162 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; in set_no_qsfp_atten()
6164 struct qib_pportdata *ppd = &dd->pport[pidx]; in set_no_qsfp_atten()
6176 if (IS_QMH(dd) || IS_QME(dd)) in set_no_qsfp_atten()
6189 for (pidx = 0; pidx < dd->num_pports; ++pidx) in set_no_qsfp_atten()
6190 if (dd->pport[pidx].link_speed_supported) in set_no_qsfp_atten()
6191 init_txdds_table(&dd->pport[pidx], 0); in set_no_qsfp_atten()
6198 struct qib_devdata *dd; in setup_txselect() local
6215 list_for_each_entry(dd, &qib_dev_list, list) in setup_txselect()
6216 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) in setup_txselect()
6217 set_no_qsfp_atten(dd, 1); in setup_txselect()
6226 static int qib_late_7322_initreg(struct qib_devdata *dd) in qib_late_7322_initreg() argument
6231 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); in qib_late_7322_initreg()
6232 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); in qib_late_7322_initreg()
6233 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); in qib_late_7322_initreg()
6234 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); in qib_late_7322_initreg()
6235 val = qib_read_kreg64(dd, kr_sendpioavailaddr); in qib_late_7322_initreg()
6236 if (val != dd->pioavailregs_phys) { in qib_late_7322_initreg()
6237 qib_dev_err(dd, in qib_late_7322_initreg()
6239 (unsigned long) dd->pioavailregs_phys, in qib_late_7322_initreg()
6244 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in qib_late_7322_initreg()
6245 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL); in qib_late_7322_initreg()
6247 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL); in qib_late_7322_initreg()
6249 qib_register_observer(dd, &sendctrl_0_observer); in qib_late_7322_initreg()
6250 qib_register_observer(dd, &sendctrl_1_observer); in qib_late_7322_initreg()
6252 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; in qib_late_7322_initreg()
6253 qib_write_kreg(dd, kr_control, dd->control); in qib_late_7322_initreg()
6260 set_no_qsfp_atten(dd, 0); in qib_late_7322_initreg()
6261 for (n = 0; n < dd->num_pports; ++n) { in qib_late_7322_initreg()
6262 struct qib_pportdata *ppd = dd->pport + n; in qib_late_7322_initreg()
6267 if (dd->flags & QIB_HAS_QSFP) in qib_late_7322_initreg()
6270 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; in qib_late_7322_initreg()
6271 qib_write_kreg(dd, kr_control, dd->control); in qib_late_7322_initreg()
6300 qib_write_kreg(ppd->dd, kr_scratch, 0); in write_7322_init_portregs()
6331 if (ppd->dd->cspec->r1) in write_7322_init_portregs()
6342 static void write_7322_initregs(struct qib_devdata *dd) in write_7322_initregs() argument
6349 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1); in write_7322_initregs()
6351 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in write_7322_initregs()
6355 if (dd->n_krcv_queues < 2 || in write_7322_initregs()
6356 !dd->pport[pidx].link_speed_supported) in write_7322_initregs()
6359 ppd = &dd->pport[pidx]; in write_7322_initregs()
6362 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6364 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6369 if (dd->num_pports > 1) in write_7322_initregs()
6370 n = dd->first_user_ctxt / dd->num_pports; in write_7322_initregs()
6372 n = dd->first_user_ctxt - 1; in write_7322_initregs()
6376 if (dd->num_pports > 1) in write_7322_initregs()
6377 ctxt = (i % n) * dd->num_pports + pidx; in write_7322_initregs()
6399 for (i = 0; i < dd->first_user_ctxt; i++) { in write_7322_initregs()
6400 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; in write_7322_initregs()
6401 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout); in write_7322_initregs()
6410 for (i = 0; i < dd->cfgctxts; i++) { in write_7322_initregs()
6414 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); in write_7322_initregs()
6422 if (dd->num_pports) in write_7322_initregs()
6423 setup_7322_link_recovery(dd->pport, dd->num_pports > 1); in write_7322_initregs()
6426 static int qib_init_7322_variables(struct qib_devdata *dd) in qib_init_7322_variables() argument
6435 ppd = (struct qib_pportdata *)(dd + 1); in qib_init_7322_variables()
6436 dd->pport = ppd; in qib_init_7322_variables()
6437 ppd[0].dd = dd; in qib_init_7322_variables()
6438 ppd[1].dd = dd; in qib_init_7322_variables()
6440 dd->cspec = (struct qib_chip_specific *)(ppd + 2); in qib_init_7322_variables()
6442 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); in qib_init_7322_variables()
6447 spin_lock_init(&dd->cspec->rcvmod_lock); in qib_init_7322_variables()
6448 spin_lock_init(&dd->cspec->gpio_lock); in qib_init_7322_variables()
6451 dd->revision = readq(&dd->kregbase[kr_revision]); in qib_init_7322_variables()
6453 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { in qib_init_7322_variables()
6454 qib_dev_err(dd, in qib_init_7322_variables()
6459 dd->flags |= QIB_PRESENT; /* now register routines work */ in qib_init_7322_variables()
6461 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); in qib_init_7322_variables()
6462 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); in qib_init_7322_variables()
6463 dd->cspec->r1 = dd->minrev == 1; in qib_init_7322_variables()
6465 get_7322_chip_params(dd); in qib_init_7322_variables()
6466 features = qib_7322_boardname(dd); in qib_init_7322_variables()
6469 sbufcnt = dd->piobcnt2k + dd->piobcnt4k + in qib_init_7322_variables()
6472 dd->cspec->sendchkenable = kmalloc(sbufcnt * in qib_init_7322_variables()
6473 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL); in qib_init_7322_variables()
6474 dd->cspec->sendgrhchk = kmalloc(sbufcnt * in qib_init_7322_variables()
6475 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL); in qib_init_7322_variables()
6476 dd->cspec->sendibchk = kmalloc(sbufcnt * in qib_init_7322_variables()
6477 sizeof(*dd->cspec->sendibchk), GFP_KERNEL); in qib_init_7322_variables()
6478 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || in qib_init_7322_variables()
6479 !dd->cspec->sendibchk) { in qib_init_7322_variables()
6480 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n"); in qib_init_7322_variables()
6485 ppd = dd->pport; in qib_init_7322_variables()
6491 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; in qib_init_7322_variables()
6492 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; in qib_init_7322_variables()
6493 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; in qib_init_7322_variables()
6495 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | in qib_init_7322_variables()
6499 dd->flags |= qib_special_trigger ? in qib_init_7322_variables()
6506 qib_7322_set_baseaddrs(dd); in qib_init_7322_variables()
6512 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; in qib_init_7322_variables()
6514 dd->cspec->hwerrmask = ~0ULL; in qib_init_7322_variables()
6517 dd->cspec->hwerrmask &= in qib_init_7322_variables()
6529 dd->skip_kctxt_mask |= 1 << pidx; in qib_init_7322_variables()
6535 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6539 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6550 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6554 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6565 dd->num_pports++; in qib_init_7322_variables()
6566 ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports); in qib_init_7322_variables()
6568 dd->num_pports--; in qib_init_7322_variables()
6590 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6602 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6615 if (ppd->dd->cspec->r1) in qib_init_7322_variables()
6623 if (!(dd->flags & QIB_HAS_QSFP)) { in qib_init_7322_variables()
6624 if (!IS_QMH(dd) && !IS_QME(dd)) in qib_init_7322_variables()
6625 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6627 dd->unit, ppd->port); in qib_init_7322_variables()
6628 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; in qib_init_7322_variables()
6633 ppd->cpspec->no_eep = IS_QMH(dd) ? in qib_init_7322_variables()
6649 dd->rcvhdrentsize = qib_rcvhdrentsize ? in qib_init_7322_variables()
6651 dd->rcvhdrsize = qib_rcvhdrsize ? in qib_init_7322_variables()
6653 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); in qib_init_7322_variables()
6656 dd->rcvegrbufsize = max(mtu, 2048); in qib_init_7322_variables()
6657 BUG_ON(!is_power_of_2(dd->rcvegrbufsize)); in qib_init_7322_variables()
6658 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); in qib_init_7322_variables()
6660 qib_7322_tidtemplate(dd); in qib_init_7322_variables()
6666 dd->rhdrhead_intr_off = in qib_init_7322_variables()
6670 init_timer(&dd->stats_timer); in qib_init_7322_variables()
6671 dd->stats_timer.function = qib_get_7322_faststats; in qib_init_7322_variables()
6672 dd->stats_timer.data = (unsigned long) dd; in qib_init_7322_variables()
6674 dd->ureg_align = 0x10000; /* 64KB alignment */ in qib_init_7322_variables()
6676 dd->piosize2kmax_dwords = dd->piosize2k >> 2; in qib_init_7322_variables()
6678 qib_7322_config_ctxts(dd); in qib_init_7322_variables()
6679 qib_set_ctxtcnt(dd); in qib_init_7322_variables()
6688 ret = init_chip_wc_pat(dd, 0); in qib_init_7322_variables()
6693 vl15off = dd->physaddr + (dd->piobufbase >> 32) + in qib_init_7322_variables()
6694 dd->piobcnt4k * dd->align4k; in qib_init_7322_variables()
6695 dd->piovl15base = ioremap_nocache(vl15off, in qib_init_7322_variables()
6696 NUM_VL15_BUFS * dd->align4k); in qib_init_7322_variables()
6697 if (!dd->piovl15base) { in qib_init_7322_variables()
6702 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ in qib_init_7322_variables()
6707 if (!dd->num_pports) { in qib_init_7322_variables()
6708 qib_dev_err(dd, "No ports enabled, giving up initialization\n"); in qib_init_7322_variables()
6712 write_7322_initregs(dd); in qib_init_7322_variables()
6713 ret = qib_create_ctxts(dd); in qib_init_7322_variables()
6714 init_7322_cntrnames(dd); in qib_init_7322_variables()
6728 if (dd->flags & QIB_HAS_SEND_DMA) { in qib_init_7322_variables()
6729 dd->cspec->sdmabufcnt = dd->piobcnt4k; in qib_init_7322_variables()
6732 dd->cspec->sdmabufcnt = 0; in qib_init_7322_variables()
6733 sbufs = dd->piobcnt4k; in qib_init_7322_variables()
6735 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - in qib_init_7322_variables()
6736 dd->cspec->sdmabufcnt; in qib_init_7322_variables()
6737 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; in qib_init_7322_variables()
6738 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ in qib_init_7322_variables()
6739 dd->last_pio = dd->cspec->lastbuf_for_pio; in qib_init_7322_variables()
6740 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? in qib_init_7322_variables()
6741 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; in qib_init_7322_variables()
6749 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) in qib_init_7322_variables()
6750 updthresh = dd->pbufsctxt - 2; in qib_init_7322_variables()
6751 dd->cspec->updthresh_dflt = updthresh; in qib_init_7322_variables()
6752 dd->cspec->updthresh = updthresh; in qib_init_7322_variables()
6755 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) in qib_init_7322_variables()
6759 dd->psxmitwait_supported = 1; in qib_init_7322_variables()
6760 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; in qib_init_7322_variables()
6762 if (!dd->ctxtcnt) in qib_init_7322_variables()
6763 dd->ctxtcnt = 1; /* for other initialization code */ in qib_init_7322_variables()
6772 struct qib_devdata *dd = ppd->dd; in qib_7322_getsendbuf() local
6776 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; in qib_7322_getsendbuf()
6779 if ((plen + 1) > dd->piosize2kmax_dwords) in qib_7322_getsendbuf()
6780 first = dd->piobcnt2k; in qib_7322_getsendbuf()
6783 last = dd->cspec->lastbuf_for_pio; in qib_7322_getsendbuf()
6785 return qib_getsendbuf_range(dd, pbufnum, first, last); in qib_7322_getsendbuf()
6811 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6815 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6819 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6825 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6837 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6844 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6849 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6853 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6857 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6861 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6865 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6869 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6873 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6877 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6937 struct qib_devdata *dd = ppd->dd; in init_sdma_7322_regs() local
6949 if (dd->num_pports) in init_sdma_7322_regs()
6950 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ in init_sdma_7322_regs()
6952 n = dd->cspec->sdmabufcnt; /* failsafe for init */ in init_sdma_7322_regs()
6953 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - in init_sdma_7322_regs()
6954 ((dd->num_pports == 1 || ppd->port == 2) ? n : in init_sdma_7322_regs()
6955 dd->cspec->sdmabufcnt); in init_sdma_7322_regs()
6976 struct qib_devdata *dd = ppd->dd; in qib_sdma_7322_gethead() local
6985 (dd->flags & QIB_HAS_SDMA_TIMEOUT); in qib_sdma_7322_gethead()
7061 static void qib_7322_initvl15_bufs(struct qib_devdata *dd) in qib_7322_initvl15_bufs() argument
7065 vl15bufs = dd->piobcnt2k + dd->piobcnt4k; in qib_7322_initvl15_bufs()
7066 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS, in qib_7322_initvl15_bufs()
7073 if (rcd->dd->num_pports > 1) { in qib_7322_init_ctxt()
7081 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; in qib_7322_init_ctxt()
7088 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, in qib_7322_txchk_change() argument
7115 le64_to_cpu(dd->pioavailregs_dma[i]); in qib_7322_txchk_change()
7130 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
7142 clear_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7152 qib_read_kreg32(dd, kr_scratch); in qib_7322_txchk_change()
7154 set_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7160 set_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7161 clear_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7163 spin_lock_irqsave(&dd->uctxt_lock, flags); in qib_7322_txchk_change()
7165 for (i = dd->first_user_ctxt; in qib_7322_txchk_change()
7166 dd->cspec->updthresh != dd->cspec->updthresh_dflt in qib_7322_txchk_change()
7167 && i < dd->cfgctxts; i++) in qib_7322_txchk_change()
7168 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && in qib_7322_txchk_change()
7169 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) in qib_7322_txchk_change()
7170 < dd->cspec->updthresh_dflt) in qib_7322_txchk_change()
7172 spin_unlock_irqrestore(&dd->uctxt_lock, flags); in qib_7322_txchk_change()
7173 if (i == dd->cfgctxts) { in qib_7322_txchk_change()
7174 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7175 dd->cspec->updthresh = dd->cspec->updthresh_dflt; in qib_7322_txchk_change()
7176 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7177 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7180 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7181 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
7188 clear_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7189 set_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7191 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7193 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { in qib_7322_txchk_change()
7194 dd->cspec->updthresh = (rcd->piocnt / in qib_7322_txchk_change()
7196 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7197 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7200 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7201 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
7203 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7211 qib_write_kreg(dd, kr_sendcheckmask + i, in qib_7322_txchk_change()
7212 dd->cspec->sendchkenable[i]); in qib_7322_txchk_change()
7215 qib_write_kreg(dd, kr_sendgrhcheckmask + i, in qib_7322_txchk_change()
7216 dd->cspec->sendgrhchk[i]); in qib_7322_txchk_change()
7217 qib_write_kreg(dd, kr_sendibpktmask + i, in qib_7322_txchk_change()
7218 dd->cspec->sendibchk[i]); in qib_7322_txchk_change()
7225 qib_read_kreg32(dd, kr_scratch); in qib_7322_txchk_change()
7230 static void writescratch(struct qib_devdata *dd, u32 val) in writescratch() argument
7232 qib_write_kreg(dd, kr_scratch, val); in writescratch()
7236 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) in qib_7322_tempsense_rd() argument
7255 struct qib_devdata *dd; in qib_init_iba7322_funcs() local
7259 dd = qib_alloc_devdata(pdev, in qib_init_iba7322_funcs()
7263 if (IS_ERR(dd)) in qib_init_iba7322_funcs()
7266 dd->f_bringup_serdes = qib_7322_bringup_serdes; in qib_init_iba7322_funcs()
7267 dd->f_cleanup = qib_setup_7322_cleanup; in qib_init_iba7322_funcs()
7268 dd->f_clear_tids = qib_7322_clear_tids; in qib_init_iba7322_funcs()
7269 dd->f_free_irq = qib_7322_free_irq; in qib_init_iba7322_funcs()
7270 dd->f_get_base_info = qib_7322_get_base_info; in qib_init_iba7322_funcs()
7271 dd->f_get_msgheader = qib_7322_get_msgheader; in qib_init_iba7322_funcs()
7272 dd->f_getsendbuf = qib_7322_getsendbuf; in qib_init_iba7322_funcs()
7273 dd->f_gpio_mod = gpio_7322_mod; in qib_init_iba7322_funcs()
7274 dd->f_eeprom_wen = qib_7322_eeprom_wen; in qib_init_iba7322_funcs()
7275 dd->f_hdrqempty = qib_7322_hdrqempty; in qib_init_iba7322_funcs()
7276 dd->f_ib_updown = qib_7322_ib_updown; in qib_init_iba7322_funcs()
7277 dd->f_init_ctxt = qib_7322_init_ctxt; in qib_init_iba7322_funcs()
7278 dd->f_initvl15_bufs = qib_7322_initvl15_bufs; in qib_init_iba7322_funcs()
7279 dd->f_intr_fallback = qib_7322_intr_fallback; in qib_init_iba7322_funcs()
7280 dd->f_late_initreg = qib_late_7322_initreg; in qib_init_iba7322_funcs()
7281 dd->f_setpbc_control = qib_7322_setpbc_control; in qib_init_iba7322_funcs()
7282 dd->f_portcntr = qib_portcntr_7322; in qib_init_iba7322_funcs()
7283 dd->f_put_tid = qib_7322_put_tid; in qib_init_iba7322_funcs()
7284 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; in qib_init_iba7322_funcs()
7285 dd->f_rcvctrl = rcvctrl_7322_mod; in qib_init_iba7322_funcs()
7286 dd->f_read_cntrs = qib_read_7322cntrs; in qib_init_iba7322_funcs()
7287 dd->f_read_portcntrs = qib_read_7322portcntrs; in qib_init_iba7322_funcs()
7288 dd->f_reset = qib_do_7322_reset; in qib_init_iba7322_funcs()
7289 dd->f_init_sdma_regs = init_sdma_7322_regs; in qib_init_iba7322_funcs()
7290 dd->f_sdma_busy = qib_sdma_7322_busy; in qib_init_iba7322_funcs()
7291 dd->f_sdma_gethead = qib_sdma_7322_gethead; in qib_init_iba7322_funcs()
7292 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; in qib_init_iba7322_funcs()
7293 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; in qib_init_iba7322_funcs()
7294 dd->f_sdma_update_tail = qib_sdma_update_7322_tail; in qib_init_iba7322_funcs()
7295 dd->f_sendctrl = sendctrl_7322_mod; in qib_init_iba7322_funcs()
7296 dd->f_set_armlaunch = qib_set_7322_armlaunch; in qib_init_iba7322_funcs()
7297 dd->f_set_cntr_sample = qib_set_cntr_7322_sample; in qib_init_iba7322_funcs()
7298 dd->f_iblink_state = qib_7322_iblink_state; in qib_init_iba7322_funcs()
7299 dd->f_ibphys_portstate = qib_7322_phys_portstate; in qib_init_iba7322_funcs()
7300 dd->f_get_ib_cfg = qib_7322_get_ib_cfg; in qib_init_iba7322_funcs()
7301 dd->f_set_ib_cfg = qib_7322_set_ib_cfg; in qib_init_iba7322_funcs()
7302 dd->f_set_ib_loopback = qib_7322_set_loopback; in qib_init_iba7322_funcs()
7303 dd->f_get_ib_table = qib_7322_get_ib_table; in qib_init_iba7322_funcs()
7304 dd->f_set_ib_table = qib_7322_set_ib_table; in qib_init_iba7322_funcs()
7305 dd->f_set_intr_state = qib_7322_set_intr_state; in qib_init_iba7322_funcs()
7306 dd->f_setextled = qib_setup_7322_setextled; in qib_init_iba7322_funcs()
7307 dd->f_txchk_change = qib_7322_txchk_change; in qib_init_iba7322_funcs()
7308 dd->f_update_usrhead = qib_update_7322_usrhead; in qib_init_iba7322_funcs()
7309 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; in qib_init_iba7322_funcs()
7310 dd->f_xgxs_reset = qib_7322_mini_pcs_reset; in qib_init_iba7322_funcs()
7311 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; in qib_init_iba7322_funcs()
7312 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; in qib_init_iba7322_funcs()
7313 dd->f_sdma_init_early = qib_7322_sdma_init_early; in qib_init_iba7322_funcs()
7314 dd->f_writescratch = writescratch; in qib_init_iba7322_funcs()
7315 dd->f_tempsense_rd = qib_7322_tempsense_rd; in qib_init_iba7322_funcs()
7317 dd->f_notify_dca = qib_7322_notify_dca; in qib_init_iba7322_funcs()
7325 ret = qib_pcie_ddinit(dd, pdev, ent); in qib_init_iba7322_funcs()
7330 ret = qib_init_7322_variables(dd); in qib_init_iba7322_funcs()
7334 if (qib_mini_init || !dd->num_pports) in qib_init_iba7322_funcs()
7343 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); in qib_init_iba7322_funcs()
7346 irq_table[i].port <= dd->num_pports) || in qib_init_iba7322_funcs()
7348 dd->rcd[i - ARRAY_SIZE(irq_table)])) in qib_init_iba7322_funcs()
7352 actual_cnt -= dd->num_pports; in qib_init_iba7322_funcs()
7355 dd->cspec->msix_entries = kzalloc(tabsize * in qib_init_iba7322_funcs()
7357 if (!dd->cspec->msix_entries) { in qib_init_iba7322_funcs()
7358 qib_dev_err(dd, "No memory for MSIx table\n"); in qib_init_iba7322_funcs()
7362 dd->cspec->msix_entries[i].msix.entry = i; in qib_init_iba7322_funcs()
7364 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries)) in qib_init_iba7322_funcs()
7365 qib_dev_err(dd, in qib_init_iba7322_funcs()
7368 dd->cspec->num_msix_entries = tabsize; in qib_init_iba7322_funcs()
7371 qib_setup_7322_interrupt(dd, 1); in qib_init_iba7322_funcs()
7374 qib_write_kreg(dd, kr_hwdiagctrl, 0); in qib_init_iba7322_funcs()
7377 qib_devinfo(dd->pcidev, "DCA enabled\n"); in qib_init_iba7322_funcs()
7378 dd->flags |= QIB_DCA_ENABLED; in qib_init_iba7322_funcs()
7379 qib_setup_dca(dd); in qib_init_iba7322_funcs()
7385 qib_pcie_ddcleanup(dd); in qib_init_iba7322_funcs()
7387 qib_free_devdata(dd); in qib_init_iba7322_funcs()
7388 dd = ERR_PTR(ret); in qib_init_iba7322_funcs()
7390 return dd; in qib_init_iba7322_funcs()
7414 struct qib_devdata *dd = ppd->dd; in set_txdds() local
7426 regidx += (dd->palign / sizeof(u64)); in set_txdds()
7432 qib_write_kreg(dd, regidx, pack_ent); in set_txdds()
7434 qib_write_kreg(ppd->dd, kr_scratch, 0); in set_txdds()
7707 *sdr_dds = txdds_sdr + ppd->dd->board_atten; in find_best_ent()
7708 *ddr_dds = txdds_ddr + ppd->dd->board_atten; in find_best_ent()
7709 *qdr_dds = txdds_qdr + ppd->dd->board_atten; in find_best_ent()
7736 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && in find_best_ent()
7741 ppd->dd->unit, ppd->port, idx); in find_best_ent()
7763 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) in init_txdds_table()
7802 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, in ahb_mod() argument
7810 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC); in ahb_mod()
7813 qib_write_kreg(dd, KR_AHB_ACC, acc); in ahb_mod()
7816 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7821 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES); in ahb_mod()
7832 qib_write_kreg(dd, KR_AHB_TRANS, trans); in ahb_mod()
7835 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7840 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n", in ahb_mod()
7845 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7855 qib_write_kreg(dd, KR_AHB_TRANS, trans); in ahb_mod()
7858 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7863 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n", in ahb_mod()
7870 qib_write_kreg(dd, KR_AHB_ACC, prev_acc); in ahb_mod()
7877 struct qib_devdata *dd = ppd->dd; in ibsd_wr_allchans() local
7882 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, in ibsd_wr_allchans()
7884 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in ibsd_wr_allchans()
7896 ppd->dd->unit, ppd->port); in serdes_7322_los_enable()
7900 ppd->dd->unit, ppd->port); in serdes_7322_los_enable()
7910 if (ppd->dd->cspec->r1) in serdes_7322_init()
7942 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; in serdes_7322_init_old()
7946 le_val = IS_QME(ppd->dd) ? 0 : 1; in serdes_7322_init_old()
7950 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); in serdes_7322_init_old()
7957 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); in serdes_7322_init_old()
7958 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); in serdes_7322_init_old()
7959 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); in serdes_7322_init_old()
7960 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); in serdes_7322_init_old()
7963 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); in serdes_7322_init_old()
7964 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); in serdes_7322_init_old()
7965 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); in serdes_7322_init_old()
7966 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); in serdes_7322_init_old()
7969 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); in serdes_7322_init_old()
7985 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_old()
7995 ppd->dd->cspec->r1 ? in serdes_7322_init_old()
8005 if (!ppd->dd->cspec->r1) { in serdes_7322_init_old()
8023 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); in serdes_7322_init_new()
8065 if (!ppd->dd->cspec->r1) { in serdes_7322_init_new()
8091 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); in serdes_7322_init_new()
8092 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); in serdes_7322_init_new()
8093 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); in serdes_7322_init_new()
8094 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); in serdes_7322_init_new()
8097 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); in serdes_7322_init_new()
8098 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); in serdes_7322_init_new()
8099 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); in serdes_7322_init_new()
8100 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); in serdes_7322_init_new()
8103 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); in serdes_7322_init_new()
8127 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), in serdes_7322_init_new()
8140 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), in serdes_7322_init_new()
8155 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; in serdes_7322_init_new()
8165 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_new()
8186 ppd->dd->cspec->r1 ? in serdes_7322_init_new()
8216 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_code()
8224 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_mode_h1()
8227 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_mode_h1()
8234 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8236 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8238 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8240 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8301 if (!ppd->dd->cspec->r1) in force_h1()
8323 static int qib_r_grab(struct qib_devdata *dd) in qib_r_grab() argument
8327 qib_write_kreg(dd, kr_r_access, val); in qib_r_grab()
8328 qib_read_kreg32(dd, kr_scratch); in qib_r_grab()
8335 static int qib_r_wait_for_rdy(struct qib_devdata *dd) in qib_r_wait_for_rdy() argument
8341 val = qib_read_kreg32(dd, kr_r_access); in qib_r_wait_for_rdy()
8348 static int qib_r_shift(struct qib_devdata *dd, int bisten, in qib_r_shift() argument
8356 ret = qib_r_wait_for_rdy(dd); in qib_r_shift()
8370 qib_write_kreg(dd, kr_r_access, val); in qib_r_shift()
8371 qib_read_kreg32(dd, kr_scratch); in qib_r_shift()
8372 ret = qib_r_wait_for_rdy(dd); in qib_r_shift()
8378 qib_write_kreg(dd, kr_r_access, val); in qib_r_shift()
8379 qib_read_kreg32(dd, kr_scratch); in qib_r_shift()
8380 ret = qib_r_wait_for_rdy(dd); in qib_r_shift()
8388 static int qib_r_update(struct qib_devdata *dd, int bisten) in qib_r_update() argument
8394 ret = qib_r_wait_for_rdy(dd); in qib_r_update()
8396 qib_write_kreg(dd, kr_r_access, val); in qib_r_update()
8397 qib_read_kreg32(dd, kr_scratch); in qib_r_update()
8500 struct qib_devdata *dd = ppd->dd; in setup_7322_link_recovery() local
8502 if (!ppd->dd->cspec->r1) in setup_7322_link_recovery()
8505 dd->cspec->recovery_ports_initted++; in setup_7322_link_recovery()
8508 if (!both && dd->cspec->recovery_ports_initted == 1) { in setup_7322_link_recovery()
8516 if (qib_r_grab(dd) < 0 || in setup_7322_link_recovery()
8517 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 || in setup_7322_link_recovery()
8518 qib_r_update(dd, BISTEN_ETM) < 0 || in setup_7322_link_recovery()
8519 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 || in setup_7322_link_recovery()
8520 qib_r_update(dd, BISTEN_AT) < 0 || in setup_7322_link_recovery()
8521 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL, in setup_7322_link_recovery()
8523 qib_r_update(dd, BISTEN_PORT_SEL) < 0 || in setup_7322_link_recovery()
8524 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 || in setup_7322_link_recovery()
8525 qib_r_update(dd, BISTEN_AT) < 0 || in setup_7322_link_recovery()
8526 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 || in setup_7322_link_recovery()
8527 qib_r_update(dd, BISTEN_ETM) < 0) in setup_7322_link_recovery()
8528 qib_dev_err(dd, "Failed IB link recovery setup\n"); in setup_7322_link_recovery()
8533 struct qib_devdata *dd = ppd->dd; in check_7322_rxe_status() local
8536 if (dd->cspec->recovery_ports_initted != 1) in check_7322_rxe_status()
8538 qib_write_kreg(dd, kr_control, dd->control | in check_7322_rxe_status()
8540 (void)qib_read_kreg64(dd, kr_scratch); in check_7322_rxe_status()
8542 fmask = qib_read_kreg64(dd, kr_act_fmask); in check_7322_rxe_status()
8549 ppd->dd->cspec->stay_in_freeze = 1; in check_7322_rxe_status()
8550 qib_7322_set_intr_state(ppd->dd, 0); in check_7322_rxe_status()
8551 qib_write_kreg(dd, kr_fmask, 0ULL); in check_7322_rxe_status()
8552 qib_dev_err(dd, "HCA unusable until powercycled\n"); in check_7322_rxe_status()
8556 qib_write_kreg(ppd->dd, kr_hwerrclear, in check_7322_rxe_status()
8560 qib_write_kreg(dd, kr_control, dd->control); in check_7322_rxe_status()
8561 qib_read_kreg32(dd, kr_scratch); in check_7322_rxe_status()
8568 qib_read_kreg32(dd, kr_scratch); in check_7322_rxe_status()