Lines Matching refs:cspec
895 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg()
897 return readq(&dd->cspec->cregbase[regno]); in read_7322_creg()
904 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg32()
906 return readl(&dd->cspec->cregbase[regno]); in read_7322_creg32()
1530 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) in qib_7322_sdma_sendctrl()
1676 errs &= dd->cspec->errormask; in handle_7322_errors()
1677 msg = dd->cspec->emsgbuf; in handle_7322_errors()
1682 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_7322_errors()
1707 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, in handle_7322_errors()
1754 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_error_tasklet()
1816 if (!ppd->dd->cspec->r1) in handle_serdes_issues()
1837 if (!ppd->dd->cspec->r1 && in handle_serdes_issues()
1852 ppd->dd->cspec->r1 ? in handle_serdes_issues()
2030 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); in qib_7322_set_intr_state()
2033 if (dd->cspec->num_msix_entries) { in qib_7322_set_intr_state()
2086 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_7322_clear_freeze()
2130 hwerrs &= dd->cspec->hwerrmask; in qib_7322_handle_hwerrors()
2145 dd->cspec->stay_in_freeze) { in qib_7322_handle_hwerrors()
2165 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_7322_handle_hwerrors()
2166 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_handle_hwerrors()
2237 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_init_hwerrors()
2243 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_7322_init_hwerrors()
2260 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2262 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2263 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_7322_armlaunch()
2514 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2517 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2545 if (ppd->dd->cspec->r1) in qib_7322_mini_quiet_serdes()
2655 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2656 extctl = dd->cspec->extctrl & (ppd->port == 1 ? in qib_setup_7322_setextled()
2670 dd->cspec->extctrl = extctl; in qib_setup_7322_setextled()
2671 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_setup_7322_setextled()
2672 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2696 dd->cspec->dca_ctrl = 0; in qib_7322_notify_dca()
2698 dd->cspec->dca_ctrl); in qib_7322_notify_dca()
2708 struct qib_chip_specific *cspec = dd->cspec; in qib_update_rhdrq_dca() local
2712 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { in qib_update_rhdrq_dca()
2715 cspec->rhdr_cpu[rcd->ctxt] = cpu; in qib_update_rhdrq_dca()
2717 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; in qib_update_rhdrq_dca()
2718 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= in qib_update_rhdrq_dca()
2722 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2724 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2725 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); in qib_update_rhdrq_dca()
2726 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_rhdrq_dca()
2733 struct qib_chip_specific *cspec = dd->cspec; in qib_update_sdma_dca() local
2738 if (cspec->sdma_cpu[pidx] != cpu) { in qib_update_sdma_dca()
2739 cspec->sdma_cpu[pidx] = cpu; in qib_update_sdma_dca()
2740 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? in qib_update_sdma_dca()
2743 cspec->dca_rcvhdr_ctrl[4] |= in qib_update_sdma_dca()
2750 (long long) cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2752 cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2753 cspec->dca_ctrl |= ppd->hw_pidx ? in qib_update_sdma_dca()
2756 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_sdma_dca()
2762 struct qib_chip_specific *cspec = dd->cspec; in qib_setup_dca() local
2765 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) in qib_setup_dca()
2766 cspec->rhdr_cpu[i] = -1; in qib_setup_dca()
2767 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2768 cspec->sdma_cpu[i] = -1; in qib_setup_dca()
2769 cspec->dca_rcvhdr_ctrl[0] = in qib_setup_dca()
2774 cspec->dca_rcvhdr_ctrl[1] = in qib_setup_dca()
2779 cspec->dca_rcvhdr_ctrl[2] = in qib_setup_dca()
2784 cspec->dca_rcvhdr_ctrl[3] = in qib_setup_dca()
2789 cspec->dca_rcvhdr_ctrl[4] = in qib_setup_dca()
2792 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2794 cspec->dca_rcvhdr_ctrl[i]); in qib_setup_dca()
2795 for (i = 0; i < cspec->num_msix_entries; i++) in qib_setup_dca()
2796 setup_dca_notifier(dd, &cspec->msix_entries[i]); in qib_setup_dca()
2848 dd->cspec->main_int_mask = ~0ULL; in qib_7322_nomsix()
2849 n = dd->cspec->num_msix_entries; in qib_7322_nomsix()
2853 dd->cspec->num_msix_entries = 0; in qib_7322_nomsix()
2856 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]); in qib_7322_nomsix()
2859 dd->cspec->msix_entries[i].msix.vector, NULL); in qib_7322_nomsix()
2860 free_cpumask_var(dd->cspec->msix_entries[i].mask); in qib_7322_nomsix()
2861 free_irq(dd->cspec->msix_entries[i].msix.vector, in qib_7322_nomsix()
2862 dd->cspec->msix_entries[i].arg); in qib_7322_nomsix()
2874 if (dd->cspec->irq) { in qib_7322_free_irq()
2875 free_irq(dd->cspec->irq, dd); in qib_7322_free_irq()
2876 dd->cspec->irq = 0; in qib_7322_free_irq()
2889 dd->cspec->dca_ctrl = 0; in qib_setup_7322_cleanup()
2890 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); in qib_setup_7322_cleanup()
2895 kfree(dd->cspec->cntrs); in qib_setup_7322_cleanup()
2896 kfree(dd->cspec->sendchkenable); in qib_setup_7322_cleanup()
2897 kfree(dd->cspec->sendgrhchk); in qib_setup_7322_cleanup()
2898 kfree(dd->cspec->sendibchk); in qib_setup_7322_cleanup()
2899 kfree(dd->cspec->msix_entries); in qib_setup_7322_cleanup()
2907 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2908 dd->cspec->gpio_mask &= ~mask; in qib_setup_7322_cleanup()
2909 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_7322_cleanup()
2910 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2970 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); in unknown_7322_ibits()
3011 if (gpiostatus & dd->cspec->gpio_mask & mask) { in unknown_7322_gpio_intr()
3033 dd->cspec->gpio_mask &= ~gpio_irq; in unknown_7322_gpio_intr()
3034 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in unknown_7322_gpio_intr()
3065 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
3078 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
3121 istat &= dd->cspec->main_int_mask; in qib_7322intr()
3433 if (!dd->cspec->num_msix_entries) { in qib_setup_7322_interrupt()
3449 dd->cspec->irq = dd->pcidev->irq; in qib_setup_7322_interrupt()
3450 dd->cspec->main_int_mask = ~0ULL; in qib_setup_7322_interrupt()
3471 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { in qib_setup_7322_interrupt()
3480 dd->cspec->msix_entries[msixnum]. in qib_setup_7322_interrupt()
3481 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1] in qib_setup_7322_interrupt()
3496 snprintf(dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3497 sizeof(dd->cspec->msix_entries[msixnum].name) in qib_setup_7322_interrupt()
3516 snprintf(dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3517 sizeof(dd->cspec->msix_entries[msixnum].name) in qib_setup_7322_interrupt()
3522 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3523 handler, 0, dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3533 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3538 dd->cspec->msix_entries[msixnum].arg = arg; in qib_setup_7322_interrupt()
3540 dd->cspec->msix_entries[msixnum].dca = dca; in qib_setup_7322_interrupt()
3541 dd->cspec->msix_entries[msixnum].rcv = in qib_setup_7322_interrupt()
3555 &dd->cspec->msix_entries[msixnum].mask, in qib_setup_7322_interrupt()
3559 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3566 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3569 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3570 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3577 dd->cspec->main_int_mask = mask; in qib_setup_7322_interrupt()
3687 msix_entries = dd->cspec->num_msix_entries; in qib_do_7322_reset()
3695 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * in qib_do_7322_reset()
3770 dd->cspec->msix_entries[i].msix.entry = i; in qib_do_7322_reset()
3788 &dd->cspec->num_msix_entries, in qib_do_7322_reset()
3789 dd->cspec->msix_entries)) in qib_do_7322_reset()
3928 if (rcd->dd->cspec->r1) in qib_7322_get_base_info()
3954 dd->cspec->numctxts = nchipctxts; in qib_7322_config_ctxts()
3987 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
4002 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
4005 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in qib_7322_config_ctxts()
4007 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); in qib_7322_config_ctxts()
4009 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, in qib_7322_config_ctxts()
4353 if (ppd->dd->cspec->r1) { in qib_7322_set_ib_cfg()
4541 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4643 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
5055 dd->cspec->ncntrs = i; in init_7322_cntrnames()
5058 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; in init_7322_cntrnames()
5060 dd->cspec->cntrnamelen = 1 + s - cntr7322names; in init_7322_cntrnames()
5061 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs in init_7322_cntrnames()
5063 if (!dd->cspec->cntrs) in init_7322_cntrnames()
5068 dd->cspec->nportcntrs = i - 1; in init_7322_cntrnames()
5069 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; in init_7322_cntrnames()
5071 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs in init_7322_cntrnames()
5085 ret = dd->cspec->cntrnamelen; in qib_read_7322cntrs()
5091 u64 *cntr = dd->cspec->cntrs; in qib_read_7322cntrs()
5094 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_7322cntrs()
5101 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_7322cntrs()
5120 ret = dd->cspec->portcntrnamelen; in qib_read_7322portcntrs()
5130 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_7322portcntrs()
5137 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_7322portcntrs()
5206 ppd->dd->cspec->r1 ? in qib_get_7322_faststats()
5220 if (!dd->cspec->num_msix_entries) in qib_7322_intr_fallback()
5250 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); in qib_7322_mini_pcs_reset()
5262 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_mini_pcs_reset()
5712 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) in qib_7322_ib_updown()
5764 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5765 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5766 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5767 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_7322_mod()
5769 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_7322_mod()
5771 dd->cspec->gpio_out = new_out; in gpio_7322_mod()
5772 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5863 dd->cspec->cregbase = (u64 __iomem *)(cregbase + in qib_7322_set_baseaddrs()
6039 if (!ret && !ppd->dd->cspec->r1) { in qsfp_7322_event()
6087 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6088 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6089 dd->cspec->gpio_mask |= mod_prs_bit; in qib_init_7322_qsfp()
6090 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_init_7322_qsfp()
6091 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_init_7322_qsfp()
6092 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6331 if (ppd->dd->cspec->r1) in write_7322_init_portregs()
6362 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6364 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6400 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; in write_7322_initregs()
6440 dd->cspec = (struct qib_chip_specific *)(ppd + 2); in qib_init_7322_variables()
6442 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); in qib_init_7322_variables()
6447 spin_lock_init(&dd->cspec->rcvmod_lock); in qib_init_7322_variables()
6448 spin_lock_init(&dd->cspec->gpio_lock); in qib_init_7322_variables()
6463 dd->cspec->r1 = dd->minrev == 1; in qib_init_7322_variables()
6472 dd->cspec->sendchkenable = kmalloc(sbufcnt * in qib_init_7322_variables()
6473 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL); in qib_init_7322_variables()
6474 dd->cspec->sendgrhchk = kmalloc(sbufcnt * in qib_init_7322_variables()
6475 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL); in qib_init_7322_variables()
6476 dd->cspec->sendibchk = kmalloc(sbufcnt * in qib_init_7322_variables()
6477 sizeof(*dd->cspec->sendibchk), GFP_KERNEL); in qib_init_7322_variables()
6478 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || in qib_init_7322_variables()
6479 !dd->cspec->sendibchk) { in qib_init_7322_variables()
6512 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; in qib_init_7322_variables()
6514 dd->cspec->hwerrmask = ~0ULL; in qib_init_7322_variables()
6517 dd->cspec->hwerrmask &= in qib_init_7322_variables()
6535 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6539 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6550 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6554 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6615 if (ppd->dd->cspec->r1) in qib_init_7322_variables()
6729 dd->cspec->sdmabufcnt = dd->piobcnt4k; in qib_init_7322_variables()
6732 dd->cspec->sdmabufcnt = 0; in qib_init_7322_variables()
6735 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - in qib_init_7322_variables()
6736 dd->cspec->sdmabufcnt; in qib_init_7322_variables()
6737 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; in qib_init_7322_variables()
6738 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ in qib_init_7322_variables()
6739 dd->last_pio = dd->cspec->lastbuf_for_pio; in qib_init_7322_variables()
6751 dd->cspec->updthresh_dflt = updthresh; in qib_init_7322_variables()
6752 dd->cspec->updthresh = updthresh; in qib_init_7322_variables()
6783 last = dd->cspec->lastbuf_for_pio; in qib_7322_getsendbuf()
6950 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ in init_sdma_7322_regs()
6952 n = dd->cspec->sdmabufcnt; /* failsafe for init */ in init_sdma_7322_regs()
6955 dd->cspec->sdmabufcnt); in init_sdma_7322_regs()
7081 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; in qib_7322_init_ctxt()
7142 clear_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7154 set_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7160 set_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7161 clear_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7166 dd->cspec->updthresh != dd->cspec->updthresh_dflt in qib_7322_txchk_change()
7170 < dd->cspec->updthresh_dflt) in qib_7322_txchk_change()
7175 dd->cspec->updthresh = dd->cspec->updthresh_dflt; in qib_7322_txchk_change()
7177 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7188 clear_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7189 set_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7193 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { in qib_7322_txchk_change()
7194 dd->cspec->updthresh = (rcd->piocnt / in qib_7322_txchk_change()
7197 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7212 dd->cspec->sendchkenable[i]); in qib_7322_txchk_change()
7216 dd->cspec->sendgrhchk[i]); in qib_7322_txchk_change()
7218 dd->cspec->sendibchk[i]); in qib_7322_txchk_change()
7355 dd->cspec->msix_entries = kzalloc(tabsize * in qib_init_iba7322_funcs()
7357 if (!dd->cspec->msix_entries) { in qib_init_iba7322_funcs()
7362 dd->cspec->msix_entries[i].msix.entry = i; in qib_init_iba7322_funcs()
7364 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries)) in qib_init_iba7322_funcs()
7368 dd->cspec->num_msix_entries = tabsize; in qib_init_iba7322_funcs()
7910 if (ppd->dd->cspec->r1) in serdes_7322_init()
7985 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_old()
7995 ppd->dd->cspec->r1 ? in serdes_7322_init_old()
8005 if (!ppd->dd->cspec->r1) { in serdes_7322_init_old()
8065 if (!ppd->dd->cspec->r1) { in serdes_7322_init_new()
8165 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_new()
8186 ppd->dd->cspec->r1 ? in serdes_7322_init_new()
8301 if (!ppd->dd->cspec->r1) in force_h1()
8502 if (!ppd->dd->cspec->r1) in setup_7322_link_recovery()
8505 dd->cspec->recovery_ports_initted++; in setup_7322_link_recovery()
8508 if (!both && dd->cspec->recovery_ports_initted == 1) { in setup_7322_link_recovery()
8536 if (dd->cspec->recovery_ports_initted != 1) in check_7322_rxe_status()
8549 ppd->dd->cspec->stay_in_freeze = 1; in check_7322_rxe_status()