Lines Matching refs:SYM_MASK
177 #define SYM_MASK(regname, fldname) ((u64) \ macro
189 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
190 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
191 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
192 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
193 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
195 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
214 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
215 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
216 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
217 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
369 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
371 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
697 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
699 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
701 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
703 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
705 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
707 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
709 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
711 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
713 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
715 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
717 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
719 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
721 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
723 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
725 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
727 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
729 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
731 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
938 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
939 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
1143 SYM_MASK(EXTStatus, MemBISTDisabled)
1145 SYM_MASK(EXTStatus, MemBISTEndTest)
1159 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1160 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1161 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1162 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1163 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1164 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1165 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1171 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1175 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1177 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1178 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1185 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1186 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1187 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1188 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1189 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1193 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1195 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1217 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1219 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1246 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1290 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1327 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1479 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); in qib_7322_sdma_sendctrl()
1481 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); in qib_7322_sdma_sendctrl()
1484 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); in qib_7322_sdma_sendctrl()
1486 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); in qib_7322_sdma_sendctrl()
1489 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); in qib_7322_sdma_sendctrl()
1491 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); in qib_7322_sdma_sendctrl()
1494 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | in qib_7322_sdma_sendctrl()
1495 SYM_MASK(SendCtrl_0, TxeAbortIbc) | in qib_7322_sdma_sendctrl()
1496 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); in qib_7322_sdma_sendctrl()
1498 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | in qib_7322_sdma_sendctrl()
1499 SYM_MASK(SendCtrl_0, TxeAbortIbc) | in qib_7322_sdma_sendctrl()
1500 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); in qib_7322_sdma_sendctrl()
1506 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); in qib_7322_sdma_sendctrl()
1517 SYM_MASK(SendCtrl_0, SDmaCleanup)); in qib_7322_sdma_sendctrl()
1523 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); in qib_7322_sdma_sendctrl()
1813 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { in handle_serdes_issues()
1819 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && in handle_serdes_issues()
1975 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) { in handle_7322_p_errors()
1982 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); in handle_7322_p_errors()
1989 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ? in handle_7322_p_errors()
1991 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, in handle_7322_p_errors()
1993 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ? in handle_7322_p_errors()
2140 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { in qib_7322_handle_hwerrors()
2176 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) | in qib_7322_handle_hwerrors()
2177 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) { in qib_7322_handle_hwerrors()
2186 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0))) in qib_7322_handle_hwerrors()
2189 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) in qib_7322_handle_hwerrors()
2304 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); in qib_set_ib_7322_lstate()
2357 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); in set_vls()
2360 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); in set_vls()
2369 ~SYM_MASK(IBCCtrlA_0, NumVLane)) | in set_vls()
2398 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_bringup_serdes()
2404 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in qib_7322_bringup_serdes()
2454 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED)); in qib_7322_bringup_serdes()
2484 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); in qib_7322_bringup_serdes()
2502 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_bringup_serdes()
2511 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); in qib_7322_bringup_serdes()
2515 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); in qib_7322_bringup_serdes()
2559 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_mini_quiet_serdes()
2574 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); in qib_7322_mini_quiet_serdes()
2725 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); in qib_update_rhdrq_dca()
2741 SYM_MASK(DCACtrlF, SendDma1DCAOPH) : in qib_update_sdma_dca()
2742 SYM_MASK(DCACtrlF, SendDma0DCAOPH)); in qib_update_sdma_dca()
2754 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) : in qib_update_sdma_dca()
2755 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable); in qib_update_sdma_dca()
2948 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2950 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
4049 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency); in qib_7322_get_ib_cfg()
4077 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ? in qib_7322_get_ib_cfg()
4198 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold); in qib_7322_set_ib_cfg()
4212 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold); in qib_7322_set_ib_cfg()
4232 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); in qib_7322_set_ib_cfg()
4235 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); in qib_7322_set_ib_cfg()
4249 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); in qib_7322_set_ib_cfg()
4378 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, in qib_7322_set_loopback()
4384 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, in qib_7322_set_loopback()
4435 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { in set_vl_weights()
4440 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); in set_vl_weights()
4544 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4546 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4548 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4550 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4552 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); in rcvctrl_7322_mod()
4554 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); in rcvctrl_7322_mod()
4567 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4685 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4687 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4689 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); in sendctrl_7322_mod()
4694 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); in sendctrl_7322_mod()
4696 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); in sendctrl_7322_mod()
4707 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4711 SYM_MASK(SendCtrl, Disarm) | i); in sendctrl_7322_mod()
4724 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) | in sendctrl_7322_mod()
4725 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) | in sendctrl_7322_mod()
4726 SYM_MASK(SendCtrl_0, TxeBypassIbc); in sendctrl_7322_mod()
4734 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | in sendctrl_7322_mod()
4738 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) in sendctrl_7322_mod()
4739 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
5244 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) | in qib_7322_mini_pcs_reset()
5245 SYM_MASK(IBPCSConfig_0, xcv_treset) | in qib_7322_mini_pcs_reset()
5246 SYM_MASK(IBPCSConfig_0, tx_rx_reset); in qib_7322_mini_pcs_reset()
5253 ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); in qib_7322_mini_pcs_reset()
5261 SYM_MASK(HwErrClear, statusValidNoEopClear)); in qib_7322_mini_pcs_reset()
5601 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) { in qib_7322_ib_updown()
5604 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) { in qib_7322_ib_updown()
5611 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) { in qib_7322_ib_updown()
5625 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) | in qib_7322_ib_updown()
5626 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk)); in qib_7322_ib_updown()
5637 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in qib_7322_ib_updown()
5888 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5889 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5890 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5891 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5892 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5893 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5894 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
6309 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); in write_7322_init_portregs()
6322 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal)); in write_7322_init_portregs()
6332 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); in write_7322_init_portregs()
6363 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); in write_7322_initregs()
6518 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) | in qib_init_7322_variables()
6519 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) | in qib_init_7322_variables()
6535 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6537 | SYM_MASK(HwErrMask, in qib_init_7322_variables()
6540 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) | in qib_init_7322_variables()
6541 SYM_MASK(IntMask, SDmaIdleIntMask_0) | in qib_init_7322_variables()
6542 SYM_MASK(IntMask, SDmaProgressIntMask_0) | in qib_init_7322_variables()
6543 SYM_MASK(IntMask, SDmaIntMask_0) | in qib_init_7322_variables()
6544 SYM_MASK(IntMask, ErrIntMask_0) | in qib_init_7322_variables()
6545 SYM_MASK(IntMask, SendDoneIntMask_0)); in qib_init_7322_variables()
6550 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6552 | SYM_MASK(HwErrMask, in qib_init_7322_variables()
6555 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) | in qib_init_7322_variables()
6556 SYM_MASK(IntMask, SDmaIdleIntMask_1) | in qib_init_7322_variables()
6557 SYM_MASK(IntMask, SDmaProgressIntMask_1) | in qib_init_7322_variables()
6558 SYM_MASK(IntMask, SDmaIntMask_1) | in qib_init_7322_variables()
6559 SYM_MASK(IntMask, ErrIntMask_1) | in qib_init_7322_variables()
6560 SYM_MASK(IntMask, SendDoneIntMask_1)); in qib_init_7322_variables()
6757 SYM_MASK(SendCtrl, SendBufAvailPad64Byte); in qib_init_7322_variables()
7023 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) || in qib_sdma_7322_busy()
7024 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) || in qib_sdma_7322_busy()
7025 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) || in qib_sdma_7322_busy()
7026 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty)); in qib_sdma_7322_busy()
7176 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7196 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7791 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7794 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7897 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); in serdes_7322_los_enable()
7901 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); in serdes_7322_los_enable()
7929 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in serdes_7322_init_old()
8027 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in serdes_7322_init_new()
8256 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) | in write_tx_serdes_param()
8257 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) | in write_tx_serdes_param()
8258 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) | in write_tx_serdes_param()
8259 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena)); in write_tx_serdes_param()
8261 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8312 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
8539 SYM_MASK(Control, FreezeMode)); in check_7322_rxe_status()
8557 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1)); in check_7322_rxe_status()
8565 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); in check_7322_rxe_status()