Lines Matching refs:SYM_LSB
182 (((value) >> SYM_LSB(regname, fldname)) & \
187 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
198 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB) macro
370 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
372 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
466 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
467 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
669 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
671 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
673 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
675 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
677 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
679 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
681 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
683 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
685 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
696 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
698 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
700 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
702 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
704 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
706 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
708 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
710 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
712 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
714 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
716 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
718 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
720 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
722 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
724 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
726 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
728 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
730 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
942 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
945 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
1151 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1166 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1168 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1169 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1172 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1173 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1176 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1180 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1181 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1294 SYM_LSB(IntMask, fldname##Mask##_0), \
1295 SYM_LSB(IntMask, fldname##Mask##_1)), \
1299 SYM_LSB(IntMask, fldname##Mask##_1), \
1300 SYM_LSB(IntMask, fldname##Mask##_0)), \
1307 SYM_LSB(IntMask, fldname##0IntMask), \
1308 SYM_LSB(IntMask, fldname##17IntMask)), \
2370 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); in set_vls()
2416 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark); in qib_7322_bringup_serdes()
2422 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod); in qib_7322_bringup_serdes()
2424 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold); in qib_7322_bringup_serdes()
2426 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold); in qib_7322_bringup_serdes()
2432 SYM_LSB(IBCCtrlA_0, MaxPktLen); in qib_7322_bringup_serdes()
2485 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); in qib_7322_bringup_serdes()
2746 SYM_LSB(DCACtrlF, SendDma1DCAOPH) : in qib_update_sdma_dca()
2747 SYM_LSB(DCACtrlF, SendDma0DCAOPH)); in qib_update_sdma_dca()
2770 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) | in qib_setup_dca()
2771 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) | in qib_setup_dca()
2772 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) | in qib_setup_dca()
2773 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt)); in qib_setup_dca()
2775 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) | in qib_setup_dca()
2776 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) | in qib_setup_dca()
2777 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) | in qib_setup_dca()
2778 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt)); in qib_setup_dca()
2780 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) | in qib_setup_dca()
2781 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) | in qib_setup_dca()
2782 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) | in qib_setup_dca()
2783 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt)); in qib_setup_dca()
2785 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) | in qib_setup_dca()
2786 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) | in qib_setup_dca()
2787 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) | in qib_setup_dca()
2788 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt)); in qib_setup_dca()
2790 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) | in qib_setup_dca()
2791 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt)); in qib_setup_dca()
3017 pins >>= SYM_LSB(EXTStatus, GPIOIn); in unknown_7322_gpio_intr()
3547 SYM_LSB(IntRedirect0, vec1); in qib_setup_7322_interrupt()
3989 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3991 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3995 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); in qib_7322_config_ctxts()
4038 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); in qib_7322_get_ib_cfg()
4043 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); in qib_7322_get_ib_cfg()
4155 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS); in qib_7322_set_ib_cfg()
4180 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE); in qib_7322_set_ib_cfg()
4184 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); in qib_7322_set_ib_cfg()
4189 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); in qib_7322_set_ib_cfg()
4200 SYM_LSB(IBCCtrlA_0, OverrunThreshold); in qib_7322_set_ib_cfg()
4214 SYM_LSB(IBCCtrlA_0, PhyerrThreshold); in qib_7322_set_ib_cfg()
4251 SYM_LSB(IBCCtrlA_0, MaxPktLen); in qib_7322_set_ib_cfg()
4414 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & in get_vl_weights()
4416 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & in get_vl_weights()
4430 SYM_LSB(LowPriority0_0, VirtualLane)) | in set_vl_weights()
4432 SYM_LSB(LowPriority0_0, Weight)); in set_vl_weights()
4564 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); in rcvctrl_7322_mod()
4578 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); in rcvctrl_7322_mod()
4580 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); in rcvctrl_7322_mod()
4582 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); in rcvctrl_7322_mod()
4584 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4586 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4736 SYM_LSB(SendCtrl, DisarmSendBuf)); in sendctrl_7322_mod()
5765 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5766 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
6088 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6311 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP); in write_7322_init_portregs()
6756 << SYM_LSB(SendCtrl, AvailUpdThld)) | in qib_init_7322_variables()
7179 SYM_LSB(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7199 << SYM_LSB(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7792 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7793 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
8264 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8267 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8270 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8273 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8313 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)