131 	struct qup_i2c_dev *qup = dev;  in qup_i2c_interrupt()  local
136 	bus_err = readl(qup->base + QUP_I2C_STATUS);  in qup_i2c_interrupt()
137 	qup_err = readl(qup->base + QUP_ERROR_FLAGS);  in qup_i2c_interrupt()
138 	opflags = readl(qup->base + QUP_OPERATIONAL);  in qup_i2c_interrupt()
140 	if (!qup->msg) {  in qup_i2c_interrupt()
142 		writel(QUP_RESET_STATE, qup->base + QUP_STATE);  in qup_i2c_interrupt()
151 		writel(qup_err, qup->base + QUP_ERROR_FLAGS);  in qup_i2c_interrupt()
157 		writel(QUP_RESET_STATE, qup->base + QUP_STATE);  in qup_i2c_interrupt()
162 		writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);  in qup_i2c_interrupt()
165 		writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);  in qup_i2c_interrupt()
168 	qup->qup_err = qup_err;  in qup_i2c_interrupt()
169 	qup->bus_err = bus_err;  in qup_i2c_interrupt()
170 	complete(&qup->xfer);  in qup_i2c_interrupt()
174 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,  in qup_i2c_poll_state_mask()  argument
185 		state = readl(qup->base + QUP_STATE);  in qup_i2c_poll_state_mask()
197 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)  in qup_i2c_poll_state()  argument
199 	return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);  in qup_i2c_poll_state()
202 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)  in qup_i2c_poll_state_valid()  argument
204 	return qup_i2c_poll_state_mask(qup, 0, 0);  in qup_i2c_poll_state_valid()
207 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)  in qup_i2c_poll_state_i2c_master()  argument
209 	return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);  in qup_i2c_poll_state_i2c_master()
212 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)  in qup_i2c_change_state()  argument
214 	if (qup_i2c_poll_state_valid(qup) != 0)  in qup_i2c_change_state()
217 	writel(state, qup->base + QUP_STATE);  in qup_i2c_change_state()
219 	if (qup_i2c_poll_state(qup, state) != 0)  in qup_i2c_change_state()
224 static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)  in qup_i2c_wait_writeready()  argument
233 		opflags = readl(qup->base + QUP_OPERATIONAL);  in qup_i2c_wait_writeready()
234 		status = readl(qup->base + QUP_I2C_STATUS);  in qup_i2c_wait_writeready()
243 		usleep_range(qup->one_byte_t, qup->one_byte_t * 2);  in qup_i2c_wait_writeready()
247 static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)  in qup_i2c_set_write_mode()  argument
252 	if (total < qup->out_fifo_sz) {  in qup_i2c_set_write_mode()
254 		writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);  in qup_i2c_set_write_mode()
255 		writel(total, qup->base + QUP_MX_WRITE_CNT);  in qup_i2c_set_write_mode()
259 		       qup->base + QUP_IO_MODE);  in qup_i2c_set_write_mode()
260 		writel(total, qup->base + QUP_MX_OUTPUT_CNT);  in qup_i2c_set_write_mode()
264 static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)  in qup_i2c_issue_write()  argument
272 	if (qup->pos == 0) {  in qup_i2c_issue_write()
280 	while (qup->pos < msg->len) {  in qup_i2c_issue_write()
282 		opflags = readl(qup->base + QUP_OPERATIONAL);  in qup_i2c_issue_write()
286 		if (qup->pos == msg->len - 1)  in qup_i2c_issue_write()
292 			val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;  in qup_i2c_issue_write()
294 			val = qup_tag | msg->buf[qup->pos];  in qup_i2c_issue_write()
297 		if (idx & 1 || qup->pos == msg->len - 1)  in qup_i2c_issue_write()
298 			writel(val, qup->base + QUP_OUT_FIFO_BASE);  in qup_i2c_issue_write()
300 		qup->pos++;  in qup_i2c_issue_write()
305 static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)  in qup_i2c_write_one()  argument
310 	qup->msg = msg;  in qup_i2c_write_one()
311 	qup->pos = 0;  in qup_i2c_write_one()
313 	enable_irq(qup->irq);  in qup_i2c_write_one()
315 	qup_i2c_set_write_mode(qup, msg);  in qup_i2c_write_one()
317 	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);  in qup_i2c_write_one()
321 	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);  in qup_i2c_write_one()
324 		ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);  in qup_i2c_write_one()
328 		qup_i2c_issue_write(qup, msg);  in qup_i2c_write_one()
330 		ret = qup_i2c_change_state(qup, QUP_RUN_STATE);  in qup_i2c_write_one()
334 		left = wait_for_completion_timeout(&qup->xfer, HZ);  in qup_i2c_write_one()
336 			writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_write_one()
341 		if (qup->bus_err || qup->qup_err) {  in qup_i2c_write_one()
342 			if (qup->bus_err & QUP_I2C_NACK_FLAG)  in qup_i2c_write_one()
343 				dev_err(qup->dev, "NACK from %x\n", msg->addr);  in qup_i2c_write_one()
347 	} while (qup->pos < msg->len);  in qup_i2c_write_one()
350 	ret = qup_i2c_wait_writeready(qup);  in qup_i2c_write_one()
353 	disable_irq(qup->irq);  in qup_i2c_write_one()
354 	qup->msg = NULL;  in qup_i2c_write_one()
359 static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)  in qup_i2c_set_read_mode()  argument
361 	if (len < qup->in_fifo_sz) {  in qup_i2c_set_read_mode()
363 		writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);  in qup_i2c_set_read_mode()
364 		writel(len, qup->base + QUP_MX_READ_CNT);  in qup_i2c_set_read_mode()
368 		       qup->base + QUP_IO_MODE);  in qup_i2c_set_read_mode()
369 		writel(len, qup->base + QUP_MX_INPUT_CNT);  in qup_i2c_set_read_mode()
373 static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)  in qup_i2c_issue_read()  argument
383 	writel(val, qup->base + QUP_OUT_FIFO_BASE);  in qup_i2c_issue_read()
387 static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)  in qup_i2c_read_fifo()  argument
393 	for (idx = 0; qup->pos < msg->len; idx++) {  in qup_i2c_read_fifo()
396 			opflags = readl(qup->base + QUP_OPERATIONAL);  in qup_i2c_read_fifo()
401 			val = readl(qup->base + QUP_IN_FIFO_BASE);  in qup_i2c_read_fifo()
403 			msg->buf[qup->pos++] = val & 0xFF;  in qup_i2c_read_fifo()
405 			msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;  in qup_i2c_read_fifo()
410 static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)  in qup_i2c_read_one()  argument
415 	qup->msg = msg;  in qup_i2c_read_one()
416 	qup->pos  = 0;  in qup_i2c_read_one()
418 	enable_irq(qup->irq);  in qup_i2c_read_one()
420 	qup_i2c_set_read_mode(qup, msg->len);  in qup_i2c_read_one()
422 	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);  in qup_i2c_read_one()
426 	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);  in qup_i2c_read_one()
428 	ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);  in qup_i2c_read_one()
432 	qup_i2c_issue_read(qup, msg);  in qup_i2c_read_one()
434 	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);  in qup_i2c_read_one()
439 		left = wait_for_completion_timeout(&qup->xfer, HZ);  in qup_i2c_read_one()
441 			writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_read_one()
446 		if (qup->bus_err || qup->qup_err) {  in qup_i2c_read_one()
447 			if (qup->bus_err & QUP_I2C_NACK_FLAG)  in qup_i2c_read_one()
448 				dev_err(qup->dev, "NACK from %x\n", msg->addr);  in qup_i2c_read_one()
453 		qup_i2c_read_fifo(qup, msg);  in qup_i2c_read_one()
454 	} while (qup->pos < msg->len);  in qup_i2c_read_one()
457 	disable_irq(qup->irq);  in qup_i2c_read_one()
458 	qup->msg = NULL;  in qup_i2c_read_one()
467 	struct qup_i2c_dev *qup = i2c_get_adapdata(adap);  in qup_i2c_xfer()  local
470 	ret = pm_runtime_get_sync(qup->dev);  in qup_i2c_xfer()
474 	writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_xfer()
475 	ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);  in qup_i2c_xfer()
480 	writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);  in qup_i2c_xfer()
488 		if (qup_i2c_poll_state_i2c_master(qup)) {  in qup_i2c_xfer()
494 			ret = qup_i2c_read_one(qup, &msgs[idx]);  in qup_i2c_xfer()
496 			ret = qup_i2c_write_one(qup, &msgs[idx]);  in qup_i2c_xfer()
501 		ret = qup_i2c_change_state(qup, QUP_RESET_STATE);  in qup_i2c_xfer()
510 	pm_runtime_mark_last_busy(qup->dev);  in qup_i2c_xfer()
511 	pm_runtime_put_autosuspend(qup->dev);  in qup_i2c_xfer()
535 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)  in qup_i2c_enable_clocks()  argument
537 	clk_prepare_enable(qup->clk);  in qup_i2c_enable_clocks()
538 	clk_prepare_enable(qup->pclk);  in qup_i2c_enable_clocks()
541 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)  in qup_i2c_disable_clocks()  argument
545 	qup_i2c_change_state(qup, QUP_RESET_STATE);  in qup_i2c_disable_clocks()
546 	clk_disable_unprepare(qup->clk);  in qup_i2c_disable_clocks()
547 	config = readl(qup->base + QUP_CONFIG);  in qup_i2c_disable_clocks()
549 	writel(config, qup->base + QUP_CONFIG);  in qup_i2c_disable_clocks()
550 	clk_disable_unprepare(qup->pclk);  in qup_i2c_disable_clocks()
557 	struct qup_i2c_dev *qup;  in qup_i2c_probe()  local
565 	qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);  in qup_i2c_probe()
566 	if (!qup)  in qup_i2c_probe()
569 	qup->dev = &pdev->dev;  in qup_i2c_probe()
570 	init_completion(&qup->xfer);  in qup_i2c_probe()
571 	platform_set_drvdata(pdev, qup);  in qup_i2c_probe()
577 		dev_err(qup->dev, "clock frequency not supported %d\n",  in qup_i2c_probe()
583 	qup->base = devm_ioremap_resource(qup->dev, res);  in qup_i2c_probe()
584 	if (IS_ERR(qup->base))  in qup_i2c_probe()
585 		return PTR_ERR(qup->base);  in qup_i2c_probe()
587 	qup->irq = platform_get_irq(pdev, 0);  in qup_i2c_probe()
588 	if (qup->irq < 0) {  in qup_i2c_probe()
589 		dev_err(qup->dev, "No IRQ defined\n");  in qup_i2c_probe()
590 		return qup->irq;  in qup_i2c_probe()
593 	qup->clk = devm_clk_get(qup->dev, "core");  in qup_i2c_probe()
594 	if (IS_ERR(qup->clk)) {  in qup_i2c_probe()
595 		dev_err(qup->dev, "Could not get core clock\n");  in qup_i2c_probe()
596 		return PTR_ERR(qup->clk);  in qup_i2c_probe()
599 	qup->pclk = devm_clk_get(qup->dev, "iface");  in qup_i2c_probe()
600 	if (IS_ERR(qup->pclk)) {  in qup_i2c_probe()
601 		dev_err(qup->dev, "Could not get iface clock\n");  in qup_i2c_probe()
602 		return PTR_ERR(qup->pclk);  in qup_i2c_probe()
605 	qup_i2c_enable_clocks(qup);  in qup_i2c_probe()
611 	writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_probe()
612 	ret = qup_i2c_poll_state_valid(qup);  in qup_i2c_probe()
616 	ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,  in qup_i2c_probe()
617 			       IRQF_TRIGGER_HIGH, "i2c_qup", qup);  in qup_i2c_probe()
619 		dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);  in qup_i2c_probe()
622 	disable_irq(qup->irq);  in qup_i2c_probe()
624 	hw_ver = readl(qup->base + QUP_HW_VERSION);  in qup_i2c_probe()
625 	dev_dbg(qup->dev, "Revision %x\n", hw_ver);  in qup_i2c_probe()
627 	io_mode = readl(qup->base + QUP_IO_MODE);  in qup_i2c_probe()
638 	qup->out_blk_sz = blk_sizes[size] / 2;  in qup_i2c_probe()
645 	qup->in_blk_sz = blk_sizes[size] / 2;  in qup_i2c_probe()
648 	qup->out_fifo_sz = qup->out_blk_sz * (2 << size);  in qup_i2c_probe()
651 	qup->in_fifo_sz = qup->in_blk_sz * (2 << size);  in qup_i2c_probe()
653 	src_clk_freq = clk_get_rate(qup->clk);  in qup_i2c_probe()
656 	qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);  in qup_i2c_probe()
663 	qup->one_byte_t = one_bit_t * 9;  in qup_i2c_probe()
665 	dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",  in qup_i2c_probe()
666 		qup->in_blk_sz, qup->in_fifo_sz,  in qup_i2c_probe()
667 		qup->out_blk_sz, qup->out_fifo_sz);  in qup_i2c_probe()
669 	i2c_set_adapdata(&qup->adap, qup);  in qup_i2c_probe()
670 	qup->adap.algo = &qup_i2c_algo;  in qup_i2c_probe()
671 	qup->adap.quirks = &qup_i2c_quirks;  in qup_i2c_probe()
672 	qup->adap.dev.parent = qup->dev;  in qup_i2c_probe()
673 	qup->adap.dev.of_node = pdev->dev.of_node;  in qup_i2c_probe()
674 	strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));  in qup_i2c_probe()
676 	pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);  in qup_i2c_probe()
677 	pm_runtime_use_autosuspend(qup->dev);  in qup_i2c_probe()
678 	pm_runtime_set_active(qup->dev);  in qup_i2c_probe()
679 	pm_runtime_enable(qup->dev);  in qup_i2c_probe()
681 	ret = i2c_add_adapter(&qup->adap);  in qup_i2c_probe()
688 	pm_runtime_disable(qup->dev);  in qup_i2c_probe()
689 	pm_runtime_set_suspended(qup->dev);  in qup_i2c_probe()
691 	qup_i2c_disable_clocks(qup);  in qup_i2c_probe()
697 	struct qup_i2c_dev *qup = platform_get_drvdata(pdev);  in qup_i2c_remove()  local
699 	disable_irq(qup->irq);  in qup_i2c_remove()
700 	qup_i2c_disable_clocks(qup);  in qup_i2c_remove()
701 	i2c_del_adapter(&qup->adap);  in qup_i2c_remove()
702 	pm_runtime_disable(qup->dev);  in qup_i2c_remove()
703 	pm_runtime_set_suspended(qup->dev);  in qup_i2c_remove()
710 	struct qup_i2c_dev *qup = dev_get_drvdata(device);  in qup_i2c_pm_suspend_runtime()  local
713 	qup_i2c_disable_clocks(qup);  in qup_i2c_pm_suspend_runtime()
719 	struct qup_i2c_dev *qup = dev_get_drvdata(device);  in qup_i2c_pm_resume_runtime()  local
722 	qup_i2c_enable_clocks(qup);  in qup_i2c_pm_resume_runtime()