Lines Matching refs:DC_WR_CH_CONF
53 #define DC_WR_CH_CONF 0x0 macro
220 reg = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
225 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
256 reg = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
258 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
267 reg = readl(dc->base + DC_WR_CH_CONF); in dc_irq_handler()
269 writel(reg, dc->base + DC_WR_CH_CONF); in dc_irq_handler()
299 val = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
301 writel(val, dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
429 priv->channels[1].base + DC_WR_CH_CONF); in ipu_dc_init()
431 priv->channels[5].base + DC_WR_CH_CONF); in ipu_dc_init()