177 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_cursor_set()
262 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_cursor_move()
598 	struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);  in vmw_framebuffer_surface_dirty()
955 	struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);  in vmw_framebuffer_dmabuf_dirty()
1007 	struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);  in vmw_framebuffer_dmabuf_pin()
1028 	struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);  in vmw_framebuffer_dmabuf_unpin()
1135 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_fb_create()
1538 int vmw_kms_write_svga(struct vmw_private *vmw_priv,  in vmw_kms_write_svga()  argument
1542 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_write_svga()
1543 		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);  in vmw_kms_write_svga()
1544 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_write_svga()
1545 		iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);  in vmw_kms_write_svga()
1546 	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);  in vmw_kms_write_svga()
1547 	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);  in vmw_kms_write_svga()
1548 	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);  in vmw_kms_write_svga()
1550 	if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {  in vmw_kms_write_svga()
1552 			  depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));  in vmw_kms_write_svga()
1559 int vmw_kms_save_vga(struct vmw_private *vmw_priv)  in vmw_kms_save_vga()  argument
1564 	vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);  in vmw_kms_save_vga()
1565 	vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);  in vmw_kms_save_vga()
1566 	vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);  in vmw_kms_save_vga()
1567 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_save_vga()
1568 		vmw_priv->vga_pitchlock =  in vmw_kms_save_vga()
1569 		  vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);  in vmw_kms_save_vga()
1570 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_save_vga()
1571 		vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +  in vmw_kms_save_vga()
1574 	if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))  in vmw_kms_save_vga()
1577 	vmw_priv->num_displays = vmw_read(vmw_priv,  in vmw_kms_save_vga()
1580 	if (vmw_priv->num_displays == 0)  in vmw_kms_save_vga()
1581 		vmw_priv->num_displays = 1;  in vmw_kms_save_vga()
1583 	for (i = 0; i < vmw_priv->num_displays; ++i) {  in vmw_kms_save_vga()
1584 		save = &vmw_priv->vga_save[i];  in vmw_kms_save_vga()
1585 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);  in vmw_kms_save_vga()
1586 		save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);  in vmw_kms_save_vga()
1587 		save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);  in vmw_kms_save_vga()
1588 		save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);  in vmw_kms_save_vga()
1589 		save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);  in vmw_kms_save_vga()
1590 		save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);  in vmw_kms_save_vga()
1591 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);  in vmw_kms_save_vga()
1592 		if (i == 0 && vmw_priv->num_displays == 1 &&  in vmw_kms_save_vga()
1600 			save->width = vmw_priv->vga_width - save->pos_x;  in vmw_kms_save_vga()
1601 			save->height = vmw_priv->vga_height - save->pos_y;  in vmw_kms_save_vga()
1608 int vmw_kms_restore_vga(struct vmw_private *vmw_priv)  in vmw_kms_restore_vga()  argument
1613 	vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);  in vmw_kms_restore_vga()
1614 	vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);  in vmw_kms_restore_vga()
1615 	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);  in vmw_kms_restore_vga()
1616 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_restore_vga()
1617 		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,  in vmw_kms_restore_vga()
1618 			  vmw_priv->vga_pitchlock);  in vmw_kms_restore_vga()
1619 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_restore_vga()
1620 		iowrite32(vmw_priv->vga_pitchlock,  in vmw_kms_restore_vga()
1621 			  vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);  in vmw_kms_restore_vga()
1623 	if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))  in vmw_kms_restore_vga()
1626 	for (i = 0; i < vmw_priv->num_displays; ++i) {  in vmw_kms_restore_vga()
1627 		save = &vmw_priv->vga_save[i];  in vmw_kms_restore_vga()
1628 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);  in vmw_kms_restore_vga()
1629 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);  in vmw_kms_restore_vga()
1630 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);  in vmw_kms_restore_vga()
1631 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);  in vmw_kms_restore_vga()
1632 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);  in vmw_kms_restore_vga()
1633 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);  in vmw_kms_restore_vga()
1634 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);  in vmw_kms_restore_vga()
1723 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_page_flip()
1799 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_gamma_set()
1828 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_du_connector_detect()
1942 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_du_connector_fill_modes()
2026 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_update_layout_ioctl()