Lines Matching refs:ioread32
58 fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); in vmw_fifo_have_3d()
62 hwversion = ioread32(fifo_mem + in vmw_fifo_have_3d()
89 caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); in vmw_fifo_have_pitchlock()
146 max = ioread32(fifo_mem + SVGA_FIFO_MAX); in vmw_fifo_init()
147 min = ioread32(fifo_mem + SVGA_FIFO_MIN); in vmw_fifo_init()
148 fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); in vmw_fifo_init()
172 if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { in vmw_fifo_ping_host()
187 dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); in vmw_fifo_release()
212 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); in vmw_fifo_is_full()
213 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); in vmw_fifo_is_full()
214 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); in vmw_fifo_is_full()
215 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); in vmw_fifo_is_full()
326 max = ioread32(fifo_mem + SVGA_FIFO_MAX); in vmw_fifo_reserve()
327 min = ioread32(fifo_mem + SVGA_FIFO_MIN); in vmw_fifo_reserve()
328 next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); in vmw_fifo_reserve()
339 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); in vmw_fifo_reserve()
443 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); in vmw_fifo_commit()
444 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); in vmw_fifo_commit()
445 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); in vmw_fifo_commit()