78 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,  in tegra_sor_writel()  function
97 	tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);  in tegra_sor_dp_train_fast()
103 	tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);  in tegra_sor_dp_train_fast()
109 	tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);  in tegra_sor_dp_train_fast()
112 	tegra_sor_writel(sor, 0, SOR_LVDS);  in tegra_sor_dp_train_fast()
118 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
123 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
130 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
143 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_dp_train_fast()
155 	tegra_sor_writel(sor, value, SOR_DP_SPARE_0);  in tegra_sor_dp_train_fast()
164 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_dp_train_fast()
179 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_dp_train_fast()
192 	tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);  in tegra_sor_super_update()
193 	tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);  in tegra_sor_super_update()
194 	tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);  in tegra_sor_super_update()
199 	tegra_sor_writel(sor, 0, SOR_STATE_0);  in tegra_sor_update()
200 	tegra_sor_writel(sor, 1, SOR_STATE_0);  in tegra_sor_update()
201 	tegra_sor_writel(sor, 0, SOR_STATE_0);  in tegra_sor_update()
211 	tegra_sor_writel(sor, value, SOR_PWM_DIV);  in tegra_sor_setup_pwm()
218 	tegra_sor_writel(sor, value, SOR_PWM_CTL);  in tegra_sor_setup_pwm()
241 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_attach()
247 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_attach()
289 	tegra_sor_writel(sor, value, SOR_PWR);  in tegra_sor_power_up()
486 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_detach()
503 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_detach()
509 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_detach()
536 	tegra_sor_writel(sor, value, SOR_PWR);  in tegra_sor_power_down()
558 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_power_down()
563 	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);  in tegra_sor_power_down()
580 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_power_down()
587 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_power_down()
592 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_power_down()
645 	tegra_sor_writel(sor, value, SOR_STATE_1);  in tegra_sor_crc_read()
649 	tegra_sor_writel(sor, value, SOR_CRC_CNTRL);  in tegra_sor_crc_read()
653 	tegra_sor_writel(sor, value, SOR_TEST);  in tegra_sor_crc_read()
659 	tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);  in tegra_sor_crc_read()
1000 	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1004 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1009 	tegra_sor_writel(sor, value, SOR_PLL_3);  in tegra_sor_encoder_mode_set()
1013 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1019 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1022 	tegra_sor_writel(sor, value, SOR_PLL_1);  in tegra_sor_encoder_mode_set()
1035 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1045 	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1051 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1055 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1059 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1073 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1081 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1085 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1092 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1117 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1122 	tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1127 	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);  in tegra_sor_encoder_mode_set()
1141 	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1151 	tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1160 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_encoder_mode_set()
1179 	tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);  in tegra_sor_encoder_mode_set()
1184 	tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);  in tegra_sor_encoder_mode_set()
1189 	tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);  in tegra_sor_encoder_mode_set()
1194 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1226 		tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1235 		tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1246 		tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_encoder_mode_set()
1298 	tegra_sor_writel(sor, value, SOR_STATE_1);  in tegra_sor_encoder_mode_set()
1306 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));  in tegra_sor_encoder_mode_set()
1312 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));  in tegra_sor_encoder_mode_set()
1318 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));  in tegra_sor_encoder_mode_set()
1324 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));  in tegra_sor_encoder_mode_set()
1329 	tegra_sor_writel(sor, value, SOR_CSTM);  in tegra_sor_encoder_mode_set()
1389 	tegra_sor_writel(sor, 0, SOR_STATE_1);  in tegra_sor_encoder_disable()